An access-sequence control scheme to enhance random-accessperformance of embedded DRAM's

An embedded DRAM enables a high data-transfer rate since it provides an on-chip wide-bus interconnection. However, the net data-transfer rate is reduced by page misses because of the inherently large row-access time of DRAM's. We previously proposed a multibank DRAM macro based on a micromodule architecture to overcome this problem. The pipelined access of the DRAM macro is especially useful for regular access in graphics applications. In this paper, we propose an access-sequence control scheme which enhances the random-access performance of embedded DRAMs. Access ID numbers, an access queue register, and a write-data buffer combined with the multibank DRAM enable out-of-sequence access which reduces the page-miss penalty during random access. In the case of four successive accesses, the estimated total access time was, respectively, reduced by up to 38 and 32% for one and two page misses, and for five successive accesses with one or two page misses, it was, respectively, reduced by up to 44 and 45%