| 电力谐波检测FFT数字逻辑的设计与实现 |
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| 引用本文： | 龚仁喜,刘丰,张海南. 电力谐波检测FFT数字逻辑的设计与实现[J]. 电力系统及其自动化学报, 2009, 21(2) |
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| 作者姓名： | 龚仁喜 刘丰 张海南 |
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| 作者单位： | 广西大学电气工程学院,南宁,530004;广西大学电气工程学院,南宁,530004;广西大学电气工程学院,南宁,530004 |
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| 基金项目： | 广西高校百名中青年学科带头人资助计划 |
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| 摘 要： | 为实现运算高速、强数据吞吐能力的快速傅里叶变换FFT(fast Fourier transform)运算处理器,探讨了基于现场可编程阵列的电力谐波检测FFT数字逻辑的设计方法.该逻辑设计采取了层次化自顶向下的设计模式,对蝶形运算、地址发生、工作存储单元等各模块进行了硬件语言描述,并通过采用复用逻辑及流水线技术,平衡了面积与速度的要求.在电力谐波检测仪原型应用的测试表明,该FFT运算逻辑可稳定运行在60MHz,单帧数据的处理时间为38 μs,流水线操作延迟为116 ns,取得了良好的应用效果.
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| 关 键 词： | 电力谐波检测 快速傅里叶变换 现场可编程门阵列 复用逻辑 流水线 |
Design and Implementation of FFT Digital Logic Utilized in Power Harmonic Detection |
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| GONG Ren-xi,LIU Feng,ZHANG Hai-nan. Design and Implementation of FFT Digital Logic Utilized in Power Harmonic Detection[J]. Proceedings of the CSU-EPSA, 2009, 21(2) |
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| Authors: | GONG Ren-xi LIU Feng ZHANG Hai-nan |
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| Affiliation: | School of Electrical Engineering;Guangxi University;Nanning 530004;China |
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| Abstract: | To realize the high-speed and great-throughput fast Fourier transform(FFT) processor a design of FFT logic utilized in power harmonic detection based on FPGA is proposed.The hierarchical top-down design method is adopted for describing the butterfly calculation,address generation,function memory hardware modules in logic design and the technique of multiplexing logic and pipeline are utilized for satisfying the requirements of the area and speed.It is shown that the FFT logic can steadily run at 60 MHz,and ... |
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| Keywords: | power harmonic analyzer fast Fourier transform(FFT) field programmable gate array(FPGA) multiplexing logic pipeline |
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