| 基于FPGA的32 Kbit/s CVSD语音编解码器的实现 |
| |
| 引用本文： | 陈普跃,潘克修.基于FPGA的32 Kbit/s CVSD语音编解码器的实现[J].电声技术,2007,31(9):30-32. |
| |
| 作者姓名： | 陈普跃 潘克修 |
| |
| 作者单位： | 解放军理工大学,通信工程学院研究生二队,江苏,南京,210007;解放军理工大学,通信工程学院研究生二队,江苏,南京,210007 |
| |
| 摘 要： | 介绍了连续可变斜率增量调制(CVSD)的基本原理,并提出了32Kbit/sCVSD语音编解码器的现场可编程门阵列(FPGA)实现方法,给出了影响CVSD性能的关键参数。该语音编解码器消耗硬件资源少,语音效果理想,适用于无线语音系统。
|
| 关 键 词： | 连续可变斜率增量调制 现场可编程门阵列 语音编码 有限脉冲响应 |
| 文章编号： | 1002-8684（2007）09-0030-03 |
| 修稿时间： | 2007-05-07 |
Implementation on 32 Kbit/s CVSD Voice Encoder and Decoder Based on FPGA |
| |
| CHEN Pu-yue,PAN Ke-xiu.Implementation on 32 Kbit/s CVSD Voice Encoder and Decoder Based on FPGA[J].Audio Engineering,2007,31(9):30-32. |
| |
| Authors: | CHEN Pu-yue PAN Ke-xiu |
| |
| Affiliation: | Postgraduate Team 2 ICE, PAL University of Science and Technology, Nanjing 210007, China |
| |
| Abstract: | The fundamental principle of encoder and decoder based on CVSD(Continuous Variable Slope Delta) modulation is introduced. A method of implementing 32 Kbit/s CVSD voice encoder and decoder based on FPGA is proposed. Key parameters to decide the performance of CVSD system are obtained. The design of encoder and decoder consumes little resource with good performance, and is fit for wireless voice system. |
| |
| Keywords: | CVSD field programmable gate array speech coding finite impulse response |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
