Low standby power state storage for sub-130-nm technologies |
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Authors: | Clark L.T. Ricci F. Biyani M. |
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Affiliation: | Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA; |
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Abstract: | Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. The approach is validated by experimental results on a 90-nm process. |
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