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Tantalum metallization and properties of silicon MOS structures under stress
Authors:B Lalevic  K Murty  H Suga  S Weissmann
Affiliation:Department of Electrical Engineering, College of Engineering, Rutgers University, P.O. Box 909, Piscataway, N.J. 08854, U.S.A.;Department of Mechanics and Materials Science, College of Engineering, Rutgers University, P.O. Box 909, Piscataway, N.J. 08854, U.S.A.
Abstract:Stresses at the surface of a silicon wafer and at the Si-SiO2 interface were induced by the sputter deposition of tantalum films. The sputtering of tantalum produced deformation of the silicon wafers by bending, and the radius of curvature was a function of the tantalum sputtering voltage and the tantalum film thickness. The magnitude of the stress induced at the silicon surface was determined from automatic Bragg angle control measurements of the radius of curvature. The surface distribution of the strain field and its distribution in the bulk of the silicon wafer were observed by the use of X-ray transmission topography. The electrical properties of the MOS capacitor were studied as a function of the induced stress. It was found that the largest changes with induced stress occur in the values of recombination time and capture cross section, while the surface state charge density Qss and the surface state density Nss are not significantly affected. Auger electron spectroscopy showed that implanted tantalum atoms diffuse through the SiO2 and reach the silicon surface.
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