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可重构阵列自主容错方法研究
引用本文:孙川,王友仁,张砦,张宇.可重构阵列自主容错方法研究[J].信息与控制,2010,39(5):568-573.
作者姓名:孙川  王友仁  张砦  张宇
作者单位:南京航空航天大学,江苏,南京,210016
基金项目:国家自然科学基金资助项目,航空科学基金资助项目 
摘    要:设计了一种具有故障自诊断和自修复能力的可重构阵列单元结构。在功能细胞单元内部实现分布式的故障自诊断,在测试到故障后,可以自主地将距故障单元最近的空闲单元进行替换,接着自动取消受故障影响的线网,并在新的布线端点间对这些线网重新布线。以4位并行乘法器为例,实验结果证明了可重构单元阵列的故障自修复能力,并验证其重构时间较短且可靠性较高。

关 键 词:数字测控系统  可重构硬件  芯片级自主容错  在线布局布线  硬件辅助布线  乘法器
收稿时间:2009-10-23
修稿时间:2010-06-08

Self Fault-tolerant Reconfigurable Array
SUN Chuan,WANG Youren,ZHANG Zhai,ZHANG Yu.Self Fault-tolerant Reconfigurable Array[J].Information and Control,2010,39(5):568-573.
Authors:SUN Chuan  WANG Youren  ZHANG Zhai  ZHANG Yu
Abstract:A self-reconfigurable array cell structure with the ability of self-testing and self-repairing is presented. The distributed fault self-diagnosing can be achieved in the function cell unit. When the fault is tested, the nearest spare cells can automatically replace the faulty cells, cancel the nets which effected by fault automatically, and reroute these nets between the new endpoints. A 4-bit parallel multiplier is chose as an example. The experiment result demonstrates self-repairing ability of self-reconfigurable cell array, and testify it requires short reconfiguration time and improves the reliability.
Keywords:Digital control and test system  Reconfigurable hardware  Chip-level self fault-tolerance  On-line layout and route  Hardware-assisted routing  Multiplier
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