| 基于FPGA的3 GHz宽带信号产生器设计 |
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| 引用本文： | 薄保林.基于FPGA的3 GHz宽带信号产生器设计[J].舰船电子对抗,2014(3):101-104. |
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| 作者姓名： | 薄保林 |
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| 作者单位： | 中国电子科技集团公司54所,石家庄050081 |
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| 摘 要： | 为适应通信对抗装备的发展,设计了能产生3GHz带宽任意波形的信号产生器。现场可编程门阵列(FPGA)产生数字波形信号,通过高速数/模转换(DAC)芯片输出模拟信号。在FPGA中采用多路并行处理算法,利用内部集成的并串转换器以及专用的复用芯片(MUX),实现DAC数据速率8Gsps,输出信号瞬时带宽3GHz以上。最后测试了信号产生器的技术指标。
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| 关 键 词： | 信号产生器 现场可编程门阵列 高速并串转换 存储器 |
Design of 3 GHz Wide-band Signal Generator Based on FPGA |
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| BO Bao-lin.Design of 3 GHz Wide-band Signal Generator Based on FPGA[J].Shipboard Electronic Countermeasure,2014(3):101-104. |
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| Authors: | BO Bao-lin |
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| Affiliation: | BO Bao-lin (The 54th Research Institute of CETC,Shijiazhuang 050081,China) |
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| Abstract: | In order to adapt the development of communication countermeasure equipments,this paper designs a signal generator,which can generate 3GHz bandwidth arbitrary waveform.The digital waveform digital is generated in field programmable gate array（FPGA）,the analog signal is sent out through a high-speed digital to analogue conversion（DAC）chip.Multipath parallel processing algorithm is used in FPGA,internal compositive parallel-to-serial converter and special multiplex（MUX）chip are used to implement 8Gsps DAC data speed and above 3GHz instantaneous bandwidth of output signal.Finally technical indexes of the signal generator is tested. |
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| Keywords: | signal generator field programmable gate array high-speed parallel-to-serial conversion memory |
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