HDLC协议IP核的设计与实现

文中针对专用ASIC芯片实现HDLC协议针对性强，使用不灵活等特点，提出了使用FPGAIP核来实现HDLC接口的设计方案。HDLCIP核包括3个模块：对外接口模块、接收模块和发送模块。IP核接收到新数据后存入接收FIFO，对外接口模块将接收到的数据通过总线将数据送入数据处理单元；当需要发送数据时数据处理单元通过总线将数据存入发送FIFO，启动发送模块将数据送出。接收和发送模块自动完成数据的”插零”及”删零”操作。仿真结果表明该IP核能够正确的接收和发送数据。该方法已在某雷达天线的同步引导数据的收发通信链路中，成功实现了双向数据通信。

Design and realization of the HDLC protocol with FPGA IP core

Using the special ASIC to realize the HDLC protocol is not flexible. The paper describes a scheme which using the FPGA IP core to realizing the HDLC protocol. The IP core includes the external interface module;receive module; transmit module. When the IP core receive new data ,it will storage the data in receive fifo. The external interface module will send out the data to the processor form the data bus. When send data, the processor will send the data to the transmit fifo,and startup the transmit module. The receive and transmit module will execute the ＂insert zero＂ and ＂delete zero＂ automatic. The emulational result indicate that the IP core can receive and transmit date correctly. The scheme has carried out the communication of the synchronous lead date in radar antenna.