| 基于ISA总线的纳秒级同步器的研制 |
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| 引用本文： | 党钊,李小群,陈骥,唐军.基于ISA总线的纳秒级同步器的研制[J].兵工自动化,2004,23(6):72-73. |
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| 作者姓名： | 党钊 李小群 陈骥 唐军 |
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| 作者单位： | 中国工程物理研究院,激光聚变研究中心,四川,绵阳,621900 |
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| 摘 要： | 基于ISA总线的纳秒级同步器采用可编程硬件延时设计,其电路采用10片MC100E195级联,17位地址选择线通过并行接口8255控制门电路.晶振脉冲分频后经8254计数并产生基准信号,送可编程门阵列MC100E195,得到20ns级的延迟范围.采用VC 对同步器硬件端口探作,通过参数设置,得到多路延时同步信号.
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| 关 键 词： | 同步器 纳秒级 可编程硬件延时 ISA总线 总线 纳秒级 同步器 ISA Bus Based 同步信号 延时设计 参数设置 硬件端口 范围 延迟 门阵列 基准信号 计数 脉冲 晶振 控制门电路 并行接口 地址选择 可编程 |
| 文章编号： | 1006-1576(2004)06-0072-02 |
| 修稿时间： | 2004年5月21日 |
Develop on NS Synchroniser Based on ISA Bus |
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| DANG Zhao,LI Xiao-qun,CHEN Ji,TANG Jun,.Develop on NS Synchroniser Based on ISA Bus[J].Ordnance Industry Automation,2004,23(6):72-73. |
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| Authors: | DANG Zhao LI Xiao-qun CHEN Ji TANG Jun |
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| Abstract: | The ns synchronizer based on ISA bus was designed with programmable hardware delay, ns hardware circuit were connected with cascade connection of 10 pieces of MC100E195, and gate circuit was controlled by 17 bit addresses choosing bus through parallel interface 8255. It makes 8254 generate a vibratory pulse and this pulse triggers a gate arrays to generate a 20 ns grade delay pulse. 20 ns grade delay pulse was sent into MC100E195, delay range of 20 ns grade was gained. The operation of synchroniser hardware port was implemented with VC , and multi-path delay synchronization signal was gained by setting parameter. |
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| Keywords: | Synchroniser NS (nanosecond) Programmable hardware delay ISA bus |
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