一种高速图像采集装置的设计

设计了一种基于NIOS II 软核处理器为系统控制核心, 以高速线阵CCD 为图像采集器件、以SDRAM 存储器为图像缓冲存储器的高速图像采集系统。采用数字技术实现了图像信号处理与数据采集、CCD 降噪的算法 以及对图像缓冲存储器的控制。采用EDA 仿真及综合工具, 对所设计的电路进行了仿真、编程和硬件调试。设计 实现了一种高速图像采集装置, 并且简化了系统的硬件结构, 提高了装置的实时性。

Design on a High-Speed Image Collecting System

The high-speed image collecting system with NIOS II soft-core processor as key component, high-speed line array CCD as image collecting component, SDRAM memory as image data buffer storage was designed. Image signal processing and data collection, noise reduction algorithm and control to image data buffer storage can be realized by digital technology. The above system has been simulated successfully by EDA software after programming and debugging with FPGA chip. Finally, system test shows that the designed system in high-speed image collection is effective, and the system hardware structure is simple, well as the real-time performance is improved greatly.