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On-Line Error Detection for Bit-Serial Multipliers in GF(2m) |
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| Authors: | Sebastian Fenn Michael Gossel Mohammed Benaissa David Taylor |
| Affiliation: | (1) Department of Electronic and Electrical Engineering, The University of Huddersfield, Queensgate, Huddersfield, West Yorkshire, HD1 3DH, UK;(2) Fault Tolerant Computing Group, The University of Potsdam, PSF 601553, 14415 Potsdam, Germany;(3) Department of Electronic and Electrical Engineering, The University of Huddersfield, Queensgate, Huddersfield, West Yorkshire, HD1 3DH, UK |
| Abstract: | In this paper error detection is applied to four finite field bit-serial multipliers. It is shown that by using parity prediction, on-line error detection can be incorporated into these multipliers with very low hardware overheads. These hardware overheads are generally independent of m and comprise only a handful of gates, so for large values of m these overheads are particularly low. The fault coverage of the presented structures has been investigated by simulation experiment and shown to range between 90% and 94.3%. |
| Keywords: | finite fields multipliers parity checking on-line error detection |
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