| 应用于微机高速线路设计的IBIS模型研究 |
| |
| 引用本文： | 蒋建军,陶恂,项湜伍.应用于微机高速线路设计的IBIS模型研究[J].信息技术,2005,29(8):115-118. |
| |
| 作者姓名： | 蒋建军 陶恂 项湜伍 |
| |
| 作者单位： | 1. 上海电机学院信息系,上海,200240
2. 上海电机学院信息系,上海,200240;上海师范大学计算机系,上海,200234 |
| |
| 摘 要： | 在微机高速系统设计中，系咎前端总线时钟为100MHz，DDR接口时钟为133MHz。介绍了IBIS模型及其模型的应用研究，列出了IBIS模型在微机系统高速设计中的一些应用，详尽地给出了时钟信号仿真的波形，从仿真结果证明了在微机高速线路设计中引入IBIS模型的重要性和必要性。
|
| 关 键 词： | IBIS模型 仿真 信号完整性 设计 |
| 文章编号： | 1009-2552(2005)08-0115-04 |
| 修稿时间： | 2004年12月27 |
Research on application of IBIS model in computer high- speed system |
| |
| Jiang Jian-jun,TAO Xun,XIANG Shi-wu.Research on application of IBIS model in computer high- speed system[J].Information Technology,2005,29(8):115-118. |
| |
| Authors: | Jiang Jian-jun TAO Xun XIANG Shi-wu |
| |
| Affiliation: | JIANG Jian-jun~1,TAO Xun~1,XIANG Shi-wu~ |
| |
| Abstract: | In the design of computer high-speed system, PSB clock is 100MHz, and DDR clock is 133 MHz. This paper introduces IBIS model and its applications, lists some applications in design of computer high-speed system, and gives the graph of clock signal simulation in detail. Simulation experiments show that it is important and necessary to introduces IBIS model into design of computer high-speed system. |
| |
| Keywords: | IBIS model simulation signal integrity design |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
