| 三维叠层DRAM封装中硅通孔开路缺陷的模拟 |
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| 引用本文： | Li Jiang,Yuxi Liu,Lian Duan,Yuan Xie,Qiang Xu. 三维叠层DRAM封装中硅通孔开路缺陷的模拟[J]. 电子工业专用设备, 2011, 40(1): 29-41 |
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| 作者姓名： | Li Jiang Yuxi Liu Lian Duan Yuan Xie Qiang Xu |
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| 作者单位： | Li Jiang,Qiang Xu(CUhk REliable computing laboratory(CURE)Department of Computer Science & Engineering,The Chinese University of Hong Kong,Shatin,N.T.,Hong Kong;Shenzhen Institutes of Advanced Technology,Chinese Academy of Science);Yuxi Liu(CUhk REliable computing laboratory(CURE)Department of Computer Science & Engineering,The Chinese University of Hong Kong,Shatin,N.T.,Hong Kong);Lian Duan,Yuan Xie(Department of Computer Science & EngineeringPennsylvania State University, USA) |
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| 基金项目： | supported in part by the General Research Fund CUHK417807 and CUHK418708 from Hong Kong SAR Research Grants Council(RGC); by National Science Foundation of China(NSFC) under grant No.60876029; a grant N CUHK417/08 from the NSFC/RGC Joint Research Scheme |
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| 摘 要： | 采用硅通孔(TSV)技术的三维堆叠封装,是一种很有前途的解决方案,可提供微处理器低延迟,高带宽的DRAM通道.然而,在3D DRAM电路中,大量的TSV互连结构,很容易产生开路缺陷和耦合噪声,从而导致了新的测试挑战.通过大量的模拟研究.本文模拟了在三维DRAM电路的字线与位线中出现的TSV开路缺陷的故障行为,它作为有效...
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| 关 键 词： | 三维堆叠封装 硅通孔 开路缺陷 耦合噪声 测试方法 诊断方法 |
Modeling TSV Open Defects in 3D-Stacked DRAM |
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| Li Jiang,Yuxi Liu,Lian Duan,Yuan Xie,Qiang Xu. Modeling TSV Open Defects in 3D-Stacked DRAM[J]. Equipment for Electronic Products Marufacturing, 2011, 40(1): 29-41 |
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| Authors: | Li Jiang Yuxi Liu Lian Duan Yuan Xie Qiang Xu |
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| Affiliation: | Li Jiang1,3,Yuxi Liu1,Lian Duan2,Yuan Xie2,and Qiang Xu1,3 (1.CUhk REliable computing laboratory(CURE) Department of Computer Science & Engineering,The Chinese University of Hong Kong,Shatin,N.T.,Hong Kong,2.Department of Computer Science & Engineering Pennsylvania State University,USA,3.Shenzhen Institutes of Advanced Technology,Chinese Academy of Science) |
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| Abstract: | Three-dimensional(3D) stacking using through silicon vias(TSVs) is a promising solution to provide low-latency and high-bandwidth DRAM access from microprocessors.The large number of TSVs implemented in 3D DRAM circuits,however,are prone to open defects and coupling noises,leading to new test challenges.Through extensive simulation studies,this paper models the faulty behavior of TSV open defects occurred on the wordlines and the bitlines of 3D DRAM circuits,which serves as the first step for efficient and ... |
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| Keywords: | 3D-stacking TSV open defects coupling noises test solutions diagnosis solutions |
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