求补舍入并行和位长自适应整数转浮点数电路设计

提出了一种实现整数转浮点数的新的设计方法 ,并且对方法的正确性给予了证明 .采用这种设计方法 ,实现了求补和舍入的合并并行 ,使关键路径的延时比常规的电路设计方案减少了 15级门 ,同时降低了电路规模 .关键路径延时的减小 ,使这一转换可以在单周期内完成 .另外 ,该方法实现了位长自适应 ,只需花费很少的电路规模和延时实现控制 ,就可以适应长整型、整型到单、双精度浮点数的转换 ,增强了电路功能 .这一设计方法同样适用于其逆转换 .该转换模块采用 Fujitsu CE71库设计 ,在 10 0 MHz主频下经仿真验证 ,结果正确 ,已经应用到实际工程中 .

CIRCUIT OF CONVERTING INTEGER TO FLOATING-POINT AND ITS PERFORMANCE OF COMPLEMENTING AND ROUNDING IN PARALLEL AND ADAPTATION OF BIT LENGTH ITSELF

A new circuit design method is proposed, which implements conversions from integer numbers to floating-point numbers, and the correctness of the method is proved. By using this method, complementing and rounding are combined and processed in parallel, so that the critical path is 15 gate delays less than common circuit structure, and the circuit scale is decreased. Because of the decreased critical path delay, the conversion can be implemented in a single cycle. In addition, bit length is adapted by itself, so the conversions from long integer or integer numbers to single or double precision floating-point numbers can be implemented, with little cost of delay and scale. The method can be applied to the contrary conversion too. The module is simulated and verified by Fujitsu CE71 under 100MHz, and is adopted by the project.