一种新型超高速高精度时钟占空比校准电路

设计了一种超高速高精度时钟占空比校准电路。采用一种新的脉冲宽度校准单元,通过控制电压调整时钟上升、下降时间来实现占空比调整。同时,设计了一种时钟放大模块,降低了占空比校准单元对输入时钟幅度的要求,提高了占空比校准精度。分析了各电路模块的作用以及对整体性能的影响。采用SMIC 65 nm CMOS工艺,在1.8 V电源电压下对各模块以及整体电路进行仿真验证。仿真结果表明,该时钟占空比校准电路能对输入频率为1～4 GHz、占空比为20%～80%的时钟进行精确校准,校准后的占空比为(50±1)%,系统稳定时间为200个输入时钟周期,功耗为10 mW。

A New Ultra High Speed and High Precision Duty Cycle Calibration Circuit

An ultra high speed and high precision duty cycle calibration circuit was designed. A new pulse width calibration unit was used to adjust the duty cycle by adjusting the clock rising and falling time via voltage controlling. At the same time, a clock amplifier was designed to reduce the amplitude requirement of the duty cycle calibration cell, and the accuracy of the duty cycle calibration cell was improved. The function of each circuit module and its effect on the overall circuit performance was analyzed. Each module and the whole circuit was simulated and verified in SMIC 65 nm CMOS process at 1.8 V power supply voltage. Simulation results showed that the proposed circuit could accurately calibrate the clocks that the duty cycle range was 20% to 80% and the input frequency range was 1 to 4 GHz. After calibration, the duty cycle was(50±1)%. The system settling time was 200 times of input clock cycles. The power consumption was 10 mW.