一种用于电流舵DAC的SDR校正技术

提出了一种基于电流舵DAC的SDR校正技术。首先采用拆分电流源的方法,增加了待校正电流源的个数。然后采用动态组合的方式,减小了电流源的失配误差,提高了DAC的静态与动态性能。与DMM校正技术相比,该SDR校正技术具有更小的残余误差、更好的静态与动态性能。采用40 nm CMOS工艺实现了一种14位200 MS/s的电流舵DAC,并进行了仿真。结果表明,通过数字校正,该DAC的INL与DNL分别从1.5 LSB和0.5 LSB降低到0.33 LSB和0.25 LSB,SFDR在整个Nyquist带宽内均大于70 dB。

An SDR Calibration Technique for Current Steering DAC

An SDR calibration technique for current steering DAC was presented. Through the splitting method, the numbers of current sources which were prepared for calibration were increased. Through the dynamic rearranging, the mismatch errors of the current sources were reduced, and the static and dynamic performances of the DAC were improved. Compared with the DMM calibration technique, the SDR calibration technique had less residual errors and better static and dynamic performances. With the proposed SDR calibration technique, an 14-bit 200 MS/s current steering DAC was designed in a 40 nm CMOS process. Simulation results showed that the SDR technique achieved a static performance of INL and DNL which was reduced from 1.5 LSB, 0.5 LSB to 0.33 LSB, 0.25 LSB, respectively. Meanwhile, the SFDR was more than 70 dB over the whole Nyquist bandwidth.