“Square Root Domain” Filter Design and Performance

This paper discusses the implementation and performance of square root domain filters, which can be considered as the CMOS equivalent of the bipolar log domain technique. The square root design methodology is based on exploiting the MOSFET large-signal square law characteristic to implement filters which are input-output linear, but operate with internally non-linear signals. The design of subcircuits required for the implementation of square root domain filters is described based on the MOSFET translinear principle, and various performance issues are discussed. Simulation and measured results are also presented to confirm the validity of this approach, which may be attractive for low-voltage operation at frequencies in the MHz range.