56 Gbit/s analogue PLL for clock recovery |
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Authors: | Schwarz V Willen B Jackel H |
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Affiliation: | Electron. Lab., Swiss Fed. Inst. of Technol. Zurich; |
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Abstract: | A clock-recovery circuit is reported that employs a phase-locked loop (PLL) at 56.88 Gbit/s, and is demonstrated by locking to a 28.44 GHz sinusoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences. To the knowledge of the authors, this is the first demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s |
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