A contribution to fast telecommunication system conception: Application to a DS-SS tracking stage improvement |
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Authors: | Cline Laurent |
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Affiliation: | aResearch Laboratory LATTIS EA 4155, IUT de Blagnac-UTM, University of Toulouse, BP 60073, 1, place G. Brassens, 31703 Blagnac, France |
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Abstract: | This paper presents an improvement of the synchronization and tracking stages of a direct sequence spread spectrum (DS-SS) communication system to reduce the acquisition time. We propose a multi-branches solution, implanted in a virtual prototype for a home automation application. The virtual prototype is based on the VHDL-AMS high-level language and the most significant physical parameters will be transferred at a high level. Finally, acquisition time simulations are compared to other classic methods and synthesis results dedicated to a real FPGA prototype are also presented. |
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Keywords: | Wireless DS-SS transceiver Multi-branches synchronization stage Virtual prototype VHDL-AMS language FPGA implementation |
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