| Abstract: | A phase‐locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog‐to‐digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power‐down mode while avoiding long wake‐up time. The PLL implemented in a 0.18 µm CMOS process occupies 0.35 mm2 active area. From a 1.8 V supply, it consumes 59 mW and 984 µW during the normal and power‐down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz. |
