C-V and C-t analysis of buried oxide layers formed by high-dose oxygen implantation

For silicon-on-insulator devices with very thin active layers, the quality of the buried oxide layer and its interface with the top silicon layer can significantly affect device performance. This study focuses on the characterization of buried oxide layers formed by high-dose oxygen implantation into Si wafers. Capacitance-voltage (C-V) and capac-itance-time (C-t) measurements were performed on the epilayer/buried oxide/substrate capacitors. From high frequency C-V measurements, data on fixed oxide charge, inter-face traps, and donor densities were obtained for both buried oxide interfaces, as well as the thickness of the buried oxide layer. From C-t measurements, minority carrier generation lifetimes were calculated for thin depletion regions on both sides of the buried oxide. The data is correlated to changes in implanted dose, anneal temperature, and anneal time.