低相噪低杂散C波段频率合成器的设计

直接数字频率合成（DDS）＋锁相环（PLL）是目前频率合成技术的常用组合方式之一。首先就DDS＋PLL的几种常用合成方式的特点进行了简单介绍，然后着重利用DDS内环分频式合成方式，实现了一种低杂散低相噪的频率合成器的设计。设计中首先在理论分析的基础上选出了合理的设计方案，然后对各项指标进行了可行性分析，尤其对输出相位噪声和组合杂散进行了详尽的阐述。最终用试验结果证明了该方案的可行性。

Design on C-band Frequency Synthesizer with Low Phase Noise and Spur Reduction

Direct digital sequence （DDS） adding phase-lock loop （PLL） is one of the usual combination modes in frequency synthesis technologies. Some application characteristics of DDS＋PLL are introduced and a design of synthesizer with low spurs and low phase noise in which DDS plays a role as a programmable fractional N divider and PLL works as an active filter is discussed in this paper. The design scheme is given based on theoretic analysis, and its feasibility is discussed. Then the phase noise and combined spurs are calculated and analyzed in detail. Finally, the experimental result proves the validity of this method.