| 关于三值维持阻塞JK触发器的研究 |
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| 引用本文： | 张炳德,徐方.关于三值维持阻塞JK触发器的研究[J].微电子学,1998,28(2):118-120. |
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| 作者姓名： | 张炳德 徐方 |
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| 作者单位： | 武汉水利电力大学电力系 |
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| 摘 要： | 提出了一种具有在输出的三值维持阻塞ＪＫ触发器电路，描述了该触发器电路的设计，对由ＴＴＬ门电路组成的试验电路进行了计算机模拟和测试，结果表明，该触发器能实现预定的功能。
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| 关 键 词： | 触发器 三值电路 时序电路 |
Development of a Ternary Edge Triggered JK Flip Flop |
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| ZHANG Bing De and XU Fang Dept.Electric Engineering,Wuhan University of Hydraulic & Electric Engineering,Wuhan,Hubei.Development of a Ternary Edge Triggered JK Flip Flop[J].Microelectronics,1998,28(2):118-120. |
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| Authors: | ZHANG Bing De and XU Fang DeptElectric Engineering Wuhan University of Hydraulic & Electric Engineering Wuhan Hubei |
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| Affiliation: | ZHANG Bing De and XU Fang Dept.Electric Engineering,Wuhan University of Hydraulic & Electric Engineering,Wuhan,Hubei 430072 |
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| Abstract: | A ternary edge triggered JK flip flop with a three rail output is proposed in the paper.The design of the circuit is described.An experimental circuit composed of TTL gates has been developed.Computer simulation and test on the experimental circuit show that the flip flop is capable of performing the predetermined logic functions. |
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| Keywords: | Flip flop Ternary logic Timing circuit |
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