| 基于FPGA的图像预处理快速算法及仿真 |
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| 引用本文： | 王德生,徐婉莹,黄新生.基于FPGA的图像预处理快速算法及仿真[J].计算机仿真,2007,24(8):320-322,326. |
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| 作者姓名： | 王德生 徐婉莹 黄新生 |
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| 作者单位： | 国防科技大学机电工程与自动化学院,湖南,长沙,410073 |
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| 摘 要： | 工程实践中,可编程逻辑器件已经越来越多的受到重视和应用.文中以DSP处理大量数据时,实时性难以达到要求入手,介绍了应用可编程逻辑器件FPGA提高程序效率、实现快速运算的一种方法,并设计了一个利用中值滤波进行图像预处理的系统,之后进行了仿真和实验验证.文章最后得到结论,采用FPGA通过用硬件逻辑来实现运算量大但相对比较简单的算法,效率要大大高于软件的多次循环,若在系统中采用DSP和FPGA合作处理数据,则可以各自发挥长处,实现快速算法.
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| 关 键 词： | 现场可编程门阵列 快速算法 数字信号处理 中值滤波 FPGA 图像预处理 快速算法 仿真 Based pretreatment Image Simulation Arithmetic 处理数据 合作 循环 软件 程序效率 比较 运算量 硬件逻辑 实验验证 系统 中值滤波 |
| 文章编号： | 1006-9348（2007）08-0320-03 |
| 修稿时间： | 2006-07-202006-07-24 |
The Fast Arithmetic and Simulation of Image pretreatment Based on FPGA |
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| WANG De-sheng,XU Wan-ying,HUANG Xin-sheng.The Fast Arithmetic and Simulation of Image pretreatment Based on FPGA[J].Computer Simulation,2007,24(8):320-322,326. |
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| Authors: | WANG De-sheng XU Wan-ying HUANG Xin-sheng |
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| Affiliation: | National University of Defense Technology, Changsha Hunan 410073, China |
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| Abstract: | In the engineering practice,Programmable Logic Device(PLD) has been recognized and applied more and more.This paper starts with the real time quality hard to achieve when the DSP deals with lots of data,and introduces a method for improving program efficiency and achieving fast arithmetic with FPGA.It designs a system for image pretreatment with median filter,and carries out simulation and validation in experiment.In conclusion,if the arithmetic for excessive but simple operation comes true through hardware logic with FPGA,the efficiency will be greatly improved.If DSP cooperates with FPGA in dealing with data in system,it may achieve fast arithmetic. |
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| Keywords: | Field programmable gate array FPGA Fast arithmetic Digital signal processing(DSP) Median filter |
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