高灵敏度GNSS接收机频率合成器设计

为了提高全球卫星导航定位系统(GNSS)接收机的灵敏度,设计低相位噪声的小数频率合成器.通过分析灵敏度与相位噪声的关系,提出新的实现方案.该方案利用品质因数增强型可变电容减小压控振荡器(VCO)相位噪声,基于CMOS双D触发器单元的多模分频器和尾电流滤波的预分频降低带内相位噪声,充、放电流自校正且互补开关切换的电荷泵和带随机化抖动的Σ Δ调制器抑制杂散.该电路在0-18 μm CMOS工艺上实现.测试结果表明：提出的频率合成器能够接收所有的GNSS信号,输出的频率调谐范围达到58%,VCO增益变化小于±21%,当偏移频率为1 MHz时, 本振(LO)相位噪声低于-121 dB,最大功耗为117 mW.提出的小数频率合成器,已成功应用于高灵敏度GNSS接收机中,在GPS模式下灵敏度达到-157 dBm.

Fractional-N frequency synthesizer for high sensitivity GNSS receiver

A low phase noise fractional-N frequency synthesizer was designed to improve the sensitivity of global navigation satellite system(GNSS) receivers. A new implementation was proposed through analyzing the relation of sensitivity and phase noise. The scheme utilized enhanced quality factor varactor to reduce phase noise from VCO, a multi-modulus divider based on dual D flip-flop cell and prescaler with tail current filter to depress in band phase noise, and a charge/discharge current auto-calibration charge pump with complementary switches and random dithering Σ Δ modulator to restrain spurs. The circuit was implemented in 0-18 μm CMOS process. Measurement results indicated that the proposed synthesizer can receive all GNSS signals with a 58% frequency tuning range, and the variation of VCO gain (KVCO) was within ±21%. Local oscillator (LO) phase noise was lower than -121 dB at 1 MHz offset, and it consumed at most 117 mW power. The proposed fractional-N frequency synthesizer was successfully applied to high sensitivity GNSS receivers; the sensitivity was -157 dBm in GPS mode．