Low-power architectural synthesis and the impact of exploiting locality

Recently there has been increased interest in the development of high-level architectural synthesis tools targeting power optimization. In this paper, we first present an overview of the various architecture synthesis tasks and analyze their influence on power consumption. A survey of previously proposed techniques is given, and areas of opportunity are identified. We next propose a new architecture synthesis technique for low-power implementation of real-time applications. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. Preserving locality results in more compact layouts, reduced usage of long high-capacitance buses, and reduced power consumption in multiplexors and buffers. Experimental results show reductions in bus and multiplexor power of up to 80% and 60%, respectively, resulting in 10–25% reduction in total power.