AEGIS: A single-chip secure processor |
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| Affiliation: | 1. Beijing Engineering Research Center of Massive Language Information Processing and Cloud Computing Application, School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China;2. Faculty of Engineering and Information Technology, University of Technology Sydney, NSW 2007, Australia;1. State Key Laboratory of Transient Optics and Photonics, Xi’an Institute of Optics and Precision Mechanics (XIOPM), Chinese Academy of Sciences (CAS), Xi’an 710119, People’s Republic of China;2. Research Center of Laser Fusion, China Academy of Engineering Physics, Mianyang 621900, People’s Republic of China;3. Key Laboratory for Physical Electronics and Devices of the Ministry of Education, Shaanxi Key Lab of Information Photonic Technique, School of Electronics & Information Engineering, Xi’an Jiaotong University, Xi’an 710049, People’s Republic of China;1. Plasma Forming Laboratory, Department of Mechanical and Materials Engineering, Florida International University, Miami, FL 33174, USA;2. Institute of Science and Technology for Ceramics (ISTEC), CNR-ISTEC, Via Granarolo 64, 48018 Faenza, Italy |
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| Abstract: | This article presents the AEGIS secure processor architecture, which enables new applications by ensuring private and authentic program execution even in the face of physical attack. Our architecture uses two new primitives to achieve physical security. First, we describe Physical Random Functions which reliably protect and share secrets in a manner that is cheaper and more secure than existing solutions based on non-volatile memory. Second, off-chip memory protection mechanisms ensure the integrity and the privacy of off-chip memory. Our processor, with its new protection mechanisms, has been implemented on an FPGA, and is fully functional. We briefly assess the cost of the security mechanisms in our processor and show that it is reasonable. |
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