A Highly Linear SAW-Less CMOS Receiver Using a Mixer With Embedded Tx Filtering for CDMA

An embedded filtering passive (EFP) mixer is used to overcome transmitter power leakage in a receiver without the use of a SAW filter. The receiver IC exhibits more than ${+}$ 60 dBm of Rx IIP$_{2}$ , 2.4 dB Rx noise figure, and ${+}$77 dB of Triple Beat (TB) with 45 MHz offset transmit leakage at 900 MHz Rx frequency while consuming only 18 mA from a 2.1 V supply. Thanks to the embedded filtering passive mixer, the proposed receiver IC shows an additional 15 dB Tx rejection compared to a conventional receiver. The additional Tx rejection improved the IIP $_{2}$ by 10 dB and TB by 30 dB. The complete receiver consists of a differential LNA employing an active post-distortion (APD), I/Q embedded filtering passive mixer, two TIAs for I/Q outputs. The fabricated receiver IC occupies 2.25 mm$^{2}$ including bonding pads, ESD devices, local oscillator (LO) input buffer, frequency divider, and mixer drivers. The receiver is fabricated using a 0.18 $mu$m CMOS process with 5 metal and 1 poly (5M1P) layer.      

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5$^{circ}$ and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.      

A 5.2-GHz CMOS receiver with 62-dB image rejection

A 5.2-GHz CMOS receiver employs a double downconversion heterodyne architecture with a local oscillator frequency of 2.6 GHz and applies offset cancellation to the baseband amplifiers. Placing the image around the zero frequency, the receiver achieves an image rejection of 62 dB with no external components while minimizing the flicker noise upconversion in the first mixing operation. Realized in a 0.25-μm digital CMOS technology, the circuit exhibits a noise figure of 6.4 dB, an IP₃ of -15 dBm, and a voltage conversion gain of 43 dB, while draining 29 mW from a 2.5-V supply     

A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs

This paper describes a radio-frequency receiver targeting spread-spectrum wireless local-area-network applications in the 2.4-GHz band. Based on a direct-conversion architecture, the receiver employs partial channel selection filtering, dc offset removal, and baseband amplification. Fabricated in a 0.6-μm CMOS technology, the receiver achieves a noise figure of 8.3 dB, IP₃ of -9 dBm, IP₂ of +22 dBm, and voltage gain of 34 dB while dissipating 80 mW from a 3-V supply     

Generalized decorrelating discrete-time rake receiver

In this paper, we introduce the generalized decorrelating discrete-time RAKE receiver (GD-DTR) for single antenna systems and extend it to multi-antenna (e.g. MIMO) systems. The GD-DTR benefits from the correlated nature of multiple access interference while being robust against channel estimation errors. It is a combination of two other advanced RAKE reception methods namely, the discrete-time version of the generalized RAKE (G-RAKE) receiver and the decorrelating discrete-time RAKE receiver (D-DTR). The G-RAKE was proposed for correlated interference mitigation. The D-DTR improves performance in the presence of channel estimation errors in diffuse channels. Our results show that the performance of the discrete-time G-RAKE (G-DTR) could be worse than a conventional discrete-time RAKE receiver (C-DTR) when there are channel estimation errors in the system. Unlike G-DTR, our proposed GD-DTR provides gains up to 0.7 dB at a raw bit error rate of 10^-2 in the presence of channel estimation errors compared to C-DTR. For the MIMO case, the gain of the MIMO GD-DTR compared to MIMO C-DTR are 1 dB and 1.1 dB at a raw bit error rate of 10^-2 in 2 transmit 2 receive antenna (2times2) and 3times3 systems respectively, if there is no correlation between the antennas. For a highly correlated receive antenna case, the gain increases to 4 dB.     

Partially coherent DS-SS performance in frequency selectivemultipath fading

The bit-error rate (BER) performance of a direct sequence spread spectrum (DS-SS) signal, operating over a multipath Rayleigh fading channel, is investigated when corrupted by phase noise as well as additive white Gaussian noise (AWGN). The phase noise arises from phase locked loop (PLL) dynamics and results in imperfect receiver phase estimates whereby the phase errors assume Tikhonov densities. The phase estimates are used by a multipath-combining RAKE receiver for demodulation. Approximate upper-bounds on the bit error probability are obtained and evaluated for different combinations of channel parameters and for various values of the average loop signal-to-noise ratio (SNR). Results indicate that for a PLL with loop SNR 10 dB above the system E _b/η₀, the degradation is less than 3 dB, and for a loop SNR of 20 dB above E_b/η₀, the degradation is less than 1 dB     

An X-Band AlGaN/GaN MMIC Receiver Front-End

This letter presents an integrated AlGaN/GaN X-band receiver front-end. This is to the authors knowledge the first published results of an integrated AlGaN/GaN MMIC receiver front-end. The receiver uses an integrated SPDT switch to reduce size, weight and cost compared to circulator based transceiver front-ends. The integrated front-end has more than 13 dB of gain and a noise figure of 3.5 dB at 11 GHz.      

A 24 GHz 6-Bit CMOS Phased-Array Receiver

This letter presents a 24 GHz 6 b phased-array receiver implemented in 0.13 mum CMOS. This design is based on a novel active vector generator that results in wideband quasi-quadrature vectors, which are used to synthesize the desired phase response. The active phase shifter has measured rms gain and phase errors of <0.5 dB and < 2.8deg at 23-24.4 GHz, resulting in a 6 b resolution. The phased-array receiver has a gain of 14 dB, a NF of 6 dB, a 3-dB gain bandwidth of 4.7 GHz and wideband input and output match. The chip consumes 30 mA from a 1.5 V supply with dimensions of 0.66 times 1.25 mm² including pads (0.5 times 1 mm² without pads).     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

Noise filtering with the nonlinear optical loop mirror

The operation of a nonlinear optical loop mirror as a passive and signal polarization independent noise filter, is investigated experimentally. Spontaneous emission not within the signal spectrum is rejected leaving a receiver noise limited solely by signal-spontaneous beat noise. The receiver power penalty caused by spontaneous emission (@BER=10^-9 (PRBS)) was improved from 3 dB to 0.4 dB by propagating a signal through the loop. A comparison between this nonlinear filtering: technique and a variable band-pass filter is also made     

A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm², or 0.23 mm² when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.     

Performance evaluation of COFDM for digital audio broadcasting. II.Effects of HPA nonlinearities

For pt. I see ibid. vol.43, no.1, p.64-75, 1997. The effects of the high power amplifier (HPA) nonlinearities on the performance of the Eureka 147 DAB system are studied by computer simulation. The performance is determined for three types of HPA: a travelling wave tube amplifier (TWTA), a solid state power amplifier (SSPA) and a perfectly linearized amplifier (PLA). Two related performance criteria are used: (a) the degradation, resulting from HPA nonlinearities, in the E_b /N₀ ratio required at the receiver to maintain a bit error rate of 10^-4 and (b) the total power degradation. These degradations are measured as a function of the HPA output backoff (OBO). The effect, on the E_b/N₀ degradation, of linearizing only the phase or only the amplitude transfer characteristic of the TWTA and the SSPA is also assessed. Correcting the phase distortion alone in both HPAs is found to reduce the E_b/N₀ degradation by less than 0.5 dB. Linearization of the amplitude characteristic alone, on the other hand, can reduce the E_b/N₀ degradation by several dBs at small OBO values (<2 dB). The optimum output backoff which minimizes the total power degradation is between 2 and 3 dB for both the TWTA and the SSPA in a terrestrial mobile channel and between 1 and 2 dB in an AWGN channel. The optimum output backoff for the PLA is 2 dB in the terrestrial channel and between 1 and 2 dB in the AWGN channel. At the optimal operation point, the power saved by linearizing the amplitude and phase characteristics of the TWTA or the SSPA is about 0.6 dB for the terrestrial mobile channel and 0.4 dB for the AWGN channel     

An IF-to-Baseband Σ∆ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range

A single-bit fifth-order complex continuous-time IF-to-baseband SigmaDelta modulator for AM/FM/IBOC receivers is presented. The input IF is 10.7 MHz and the sampling frequency is 41.7 MHz. The modulator achieves a dynamic range of 118dB in AM mode (3 kHz BW), 98dB in FM mode (200 kHz BW), and 86dB in IBOC mode (500 kHz BW). The modulator's high dynamic range enables the realization of an AM radio receiver without a VGA and without an AM channel-selection filter, thereby reducing system complexity and cost. The elimination of the VGA also improves the sensitivity and the overall noise figure of the receiver. The modulator's spurious free dynamic range is 88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in a one-poly five-metal 0.18-mum CMOS process with an active area of 6.0mm². It consumes 210 mW from a 1.8-V supply     

Adaptive Blocker Rejection Continuous-Time $Sigma Delta $ ADC for Mobile WiMAX Applications

An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a worldwide inter-operability for microwave access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 mus, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving - 22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metal-insulator-metal (MIM) capacitor, CMOS technology, occupying 1.5 times 0.9 mm² silicon area.     

0.5-V 5.6-GHz CMOS Receiver Subsystem

The building blocks of a 0.5-V receiver, including a receiver front-end and a low-pass filter (LPF), are fabricated using 0.18- $mu{hbox{m}}$ CMOS technology. At 5.6 GHz, the receiver front-end achieves a voltage gain of 17.1 dB and a noise figure of 8.7 dB, while dissipating at 19.4 mW. The fifth-order low-pass Chebyshev filter achieves a corner frequency of 2.6 MHz and an input-referred noise of 28.5 nV/sqrt (Hz) at 6.8 mW. The receiver front-end is further integrated with the LPFs to form a highly integrated receiver subsystem at ultra-low voltage.      

A high-temperature superconducting duplexer for cellularbase-station applications

This paper presents a recent investigation of a high-temperature superconducting (HTS) duplexer for cellular base-station applications. The duplexer consists of two HTS hybrids and two HTS bandstop filters. The principle and design of the duplexer are described, The components of the duplexer were fabricated individually using double-sided YBa₂Cu₃O₇ (YBCO) thin films on LaAlO ₃ (LAO) substrates. The substrate size for each of the hybrids was 0.5×22.5×15.5 mm, while each of the bandstop filters had a substrate size of 0.5×13×38 mm. Experiments were performed both with a test housing in a liquid-nitrogen cooler at a temperature of 80 K and in an encapsulated RF connector ring in a vacuum cooler at 55 K, The measured insertion loss was less than 0.3 dB both from the antenna to receiver ports over a receive band of 1770-1785 MHz and from the transmitter to antenna ports over a transmit band of 1805-1880 MHz. The isolation between the transmitter and receiver was measured to be greater than 35 dB, Good measured results were also obtained for the encapsulated duplexer with the maximum insertion loss of 1.15 dB, the additional loss being due to the microstrip feed lines actress the vacuum space, and the minimum isolation of about 30 dB     

Impact of laser phase noise on the performance of a {3×3}phase and polarization diversity optical homodyne DPSK receiver

An analysis of the impact of laser phase noise on the performance of a {3×3} phase- and polarization-diversity differential phase-shift keying (DPSK) receiver is done for the phase and shot-noise limited case. The results show that, for zero laser linewidths, the maximal signal power penalty of the {3×3} phase- and polarization-diversity DPSK receiver with respect to the conventional heterodyne DPSK receiver is approximately 0.7 dB for P_e =10^-9. For nonzero laser linewidths, it appears that, depending on the laser linewidth, for large signal-to-noise ratios the performance of the analyzed {3×3} phase- and polarization-diversity DPSK receiver is close to that of the ideal conventional heterodyne DPSK receiver. For a rectangular intermediate-frequency filter, the maximum allowable normalized laser linewidth (Δυ×T) for the (3×3) phase and polarization diversity DPSK receiver is found to be approximately 0.46% for a power penalty of 1 dB     

High-dynamic-range airborne tracking and fire control radarsubsystem

Two high-dynamic-range receiver subsystems for use in airborne radar fire control and tracking applications are described. The X -band dual-channel monopulse tracking receiver operates at 9.36±0.290 GHz with a 6-dB noise figure and a linear instantaneous dynamic range of 42 dB. A total of 80 dB of RF and IF gain control is programmable with less than ±15° phase and ±1 dB amplitude tracking errors. The Doppler radar receiver operates at 9.3±0.15 GHz and has a 4.6-dB noise figure with ⩾80 dB of instantaneous dynamic range. An 18-dB sensitivity time control (STC) circuit and a 60-dB dump attenuator allow close-in target reception     

Performance characteristics of a 300-GHz radiometer and some atmospheric attenuation measurements

A 300-GHz Dicke-type superheterodyne radiometer receiver was used for measurements of atmospheric attenuation of electromagnetic waves over an open path at frequencies near 300 GHz. The average measured values of horizontal attenuation at 304 GHz and 316 GHz, presumably due to atmospheric water vapor absorption, were, respectively, 3.35 dB/km and 5.55 dB/km per g/m³of water vapor density. Absorption variations at 304 GHz with respect to water vapor density were shown in the measured results. The variation of the effective zenith sky temperature with respect to atmospheric water vapor density was also determined. The minimum detectable temperature difference(Delta T)_{min}, was obtained by measuring the rms value of noise in the receiver output. The best value achieved was3.16degK. Based on this result, the receiver noise figure and the mixer conversion loss were determined indirectly. The results were 31.4 dB and 22.9 dB, respectively. A blackbody radiation source served to calibrate the radiometer.     

A 9 mW Highly-Digitized 802.15.4 Receiver Using Bandpass $SigmaDelta$ ADC and IF Level Detection

A low power (9 mW) highly-digitized 2.4 GHz receiver for sensor network applications (IEEE 802.15.4 LR-WPAN) is realized by a 0.18 $mu{rm m}$ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time (CT) bandpass $SigmaDelta$ modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed $SigmaDelta$ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range (DR) of the overall system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.