应用于逻辑核的BIST关键技术研究

随着集成电路工艺进入深亚微米阶段后,电路复杂度的不断提高,特别是片上系统的不断发展,主要包括验证测试和制造测试的芯片测试,正在面临着巨大的挑战,传统的使用自动测试设备的测试方法越来越不能满足测试需要。各种用于提高芯片可测试性的可测性设计方法被提出,其中逻辑内建自测试方法已经被证明为大规模集成电路（VLS1）和SOC测试的一项有效的可测试性设计方法。文章首先对Logic BIST的基本原理结构进行介绍,然后对其在实践应用中的一些难点问题进行详细分析,最后给出针对一款高性能通用处理器实验的结果。     

Testing and built-in self-test – A survey

As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This built-in self-test (BIST) approach not only offers economic benefits but also interesting technical opportunities with respect to hierarchical testing and the reuse of test logic during the application of the circuit.Starting with an overview of test problems, test applications and terminology this survey reviews common test methods and analyzes the basic test procedure. The concept of BIST is introduced and discussed, BIST strategies for random logic as well as for structured logic are shown.     

A low-cost concurrent BIST scheme for increased dependability

Built-in self-test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and in offline BIST schemes. An important measure of the quality of an input vector monitoring concurrent BIST scheme is the time required to complete the concurrent test, termed concurrent test latency. In this paper, a new input vector monitoring concurrent BIST technique for combinational circuits is presented which is shown to be significantly more efficient than the input vector monitoring techniques proposed to date with respect to concurrent test latency and hardware overhead trade-off, for low values of the hardware overhead.     

A loop-based apparatus for at-speed self-testing

At-speed testing using external tester requires an expensive equipment,thus built-in self-test(BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing.The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead.This paper presents an improved loop-based BIST scheme,in which a configurable MISR (multiple-input signature register)is used to generate test-pair sequences.The structure and operation modes of the BIST scheme are described.The topological properties of the state-transition-graph of the proposed BIST scheme are analyzed.Based on it ,an approach to design and efficiently implement the proposed BIST scheme is developed.Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.     

基于二维运动机械臂的移动设备测试研究

现有移动设备测试自动化框架大多是侵入性的,故而难以用于一些系统封闭的设备.非侵入式测试可以大大扩展自动测试技术的应用范围.由此,提出了一种基于二维运动机械臂的新型移动设备测试自动化技术.该技术使用可视化脚本表达测试动作,提出视觉引擎驱动二维运动机械臂自动对移动设备进行非侵入性的测试.案例研究表明该框架具有较高的测试执行准确度和速度,有良好的实用价值.     

On-Line Testing of Lab-on-Chip Using Reconfigurable Digital-Microfluidic Compactors

Dependability is an important system attribute for microfluidic lab-on-chip devices. On-line testing offers a promising method for detecting defects, fluidic abnormalities, and bioassay malfunctions during chip operation. However, previous techniques for reading test outcomes and analyzing pulse sequences are cumbersome, sensitive to the calibration of capacitive sensors, and error-prone. We present a built-in self-test (BIST) method for on-line testing of digital microfluidic lab-on-chip. This method utilizes microfluidic compactors based on droplet-based AND gates, which are implemented using digital microfluidics. An optimization method is proposed to schedule logic AND operations in the compactor to minimize the end time for the compaction procedure. Dynamic reconfiguration of these compactors ensures low area overhead and it allows BIST to be interleaved with bioassays in functional mode. We evaluate the on-line testing method using a multiplexed in vitro diagnostics bioassay.     

The Design of Dedicated 32-Bit Processors

NTT has developed two CMOS 32-bit processor VLSI families dedicated to communication systems: DIPS is for on-line information processing, while DEX is for an electronic switching system. The design methodology uses a hierarchical design technique, a common design language and database, and automated layout based on a standard cell approach. Gate density was improved by a factor of 1.3 using a superblock technique. Design for testability is primarily built-in test using a scan path method.     

一种基于轮流扫描捕获的低功耗低费用BIST方法

过高的测试功耗和过长的测试应用时间是基于伪随机内建自测试(BIST)的扫描测试所面临的两大主要问题.提出了一种基于扫描子链轮流扫描捕获的BIST方法.在提出的方法中,每条扫描链被划分成N(N>1)条子链,使用扫描链阻塞技术,同一时刻每条扫描链中只有一条扫描子链活跃,扫描子链轮流进行扫描和捕获,有效地降低了扫描移位和响应捕获期间扫描单元的翻转频率.同时,为检测抗随机故障提出了一种适用于所提出测试方法的线性反馈移位寄存器(LFSR)种子产生算法.在ISCAS89基准电路上进行的实验表明,提出的方案不但降低约(N-1)?N的平均功耗和峰值功耗,而且显著地减少随机测试的测试应用时间和LFSR重播种的种子存储量.     

Built-in Self Testing of Embedded Memories

The authors present a built-in self-test (BIST) method for testing embedded memories. Two algorithms are proposed for self-testing of embedded bedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults. The hardware implementation of the methods requires a hardware test-pattern generator, which produces address, data, and read/write inputs. The output responses of the memory can be compressed by using a parallel input signature analyzer, or they can be compared with expected responses by an output comparator. The layout of memories has been considered in the design of additional BIST circuitry. The authors conclude by evaluating the two schemes on the basis of area overhead, performance degradation, fault coverage, test application time, and testing of self-test circuitry. The BIST overhead is very low and test time is quite short. Six devices, with one of the test schemes, have been manufactured and are in the field.     

Implementation of moving TDM slots for voice transmission on Ethernet

The concept of moving time division multiplex (TDM) slots has been suggested as a method of avoiding collisions on an Ethernet system carrying voice and data packets. This paper describes a technique for implementing a type of moving TDM slot system with currently available VLSI Ethernet devices. The technique is hardware based and has the advantage of operating within the standard Ethernet parameters and of having a low cost of implementation.     

Built-in self-testing of random-access memories

Built-in self-test (BIST) methods are examined, including the fault models and the test algorithms on which the BIST implementations are based. The notion of generic test architectures suitable for implementing a wide variety of test algorithms is introduced. A taxonomy for test architectures is provided and used to categorize BIST implementations, and important implementations are surveyed. It is demonstrated that BIST is a viable solution to the problem of testing large memories and that approaches based on test architectures rather than on test algorithms are more versatile and will likely predominate in the future     

Macro Testing: Unifying IC And Board Test

Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexity in both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couples both types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustom VLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term ?macro testing.? The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macros and the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro tests into a chip test.     

基于FPGA的内建自测试的实现研究

内建自测试技术源于激励-响应-比较的测试机理,信号可以通过边界扫描传输到芯片引脚,因而即使BIST本身发生故障也可以通过边界扫描进行检测;为了解决大规模SOC芯片设计中BIST测试时间长和消耗面积大的问题,提出了一种用FPGA实现BIST电路的方法,对测试向量发生器、被测内核和特征分析器进行了研究;通过对被测内核注入故障,然后将正常电路和注入故障后的电路分别进行仿真,比较正常响应和实际响应的特征值,如果相等则认为没有故障,否则发生了特定的故障;利用ModelSim SE 6.1f软件仿真结果表明了该方法的正确有效性和快速性。     

A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation

We present a new parallel semiconductor device simulation using the dynamic load balancing approach. This semiconductor device simulation based on the adaptive finite volume method with a posteriori error estimation has been developed and successfully implemented on a 16-PC Linux cluster with a message passing interface library. A constructive monotone iterative technique is also applied for solution of the system of nonlinear algebraic equations. Two different parallel versions of the algorithm to perform a complete device simulation are proposed. The first is a dynamic parallel domain decomposition approach, and the second is a parallel current-voltage characteristic points simulation. This implementation shows that a well-designed load balancing simulation can significantly reduce the execution time up to an order of magnitude. Compared with the measured data, numerical results on various submicron VLSI devices are presented, to show the accuracy and efficiency of the method.     

A Universal BIST Approach for Virtex-Ultrascale Architecture

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs’ capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.     

Search-based automated testing of continuous controllers: Framework,tool support,and case studies

ContextTesting and verification of automotive embedded software is a major challenge. Software production in automotive domain comprises three stages: Developing automotive functions as Simulink models, generating code from the models, and deploying the resulting code on hardware devices. Automotive software artifacts are subject to three rounds of testing corresponding to the three production stages: Model-in-the-Loop (MiL), Software-in-the-Loop (SiL) and Hardware-in-the-Loop (HiL) testing.ObjectiveWe study testing of continuous controllers at the Model-in-Loop (MiL) level where both the controller and the environment are represented by models and connected in a closed loop system. These controllers make up a large part of automotive functions, and monitor and control the operating conditions of physical devices.MethodWe identify a set of requirements characterizing the behavior of continuous controllers, and develop a search-based technique based on random search, adaptive random search, hill climbing and simulated annealing algorithms to automatically identify worst-case test scenarios which are utilized to generate test cases for these requirements.ResultsWe evaluated our approach by applying it to an industrial automotive controller (with 443 Simulink blocks) and to a publicly available controller (with 21 Simulink blocks). Our experience shows that automatically generated test cases lead to MiL level simulations indicating potential violations of the system requirements. Further, not only does our approach generate significantly better test cases faster than random test case generation, but it also achieves better results than test scenarios devised by domain experts. Finally, our generated test cases uncover discrepancies between environment models and the real world when they are applied at the Hardware-in-the-Loop (HiL) level.ConclusionWe propose an automated approach to MiL testing of continuous controllers using search. The approach is implemented in a tool and has been successfully applied to a real case study from the automotive domain.     

Automated test‐data generation for exception conditions

This paper presents a technique for automatically generating test‐data to test exceptions. The approach is based on the application of a dynamic global optimization based search for the required test‐data. The authors' work has focused on test‐data generation for safety‐critical systems. Such systems must be free from anomalous and uncontrolled behaviour. Typically, it is easier to prove the absence of any exceptions than proving that the exception handling is safe. A process for integrating automated testing with exception freeness proofs is presented as a way forward for tackling the special needs of safety critical systems. The results of a number of simple case‐studies are presented and show the technique to be effective. The major result shows the application of the technique to a commercial aircraft engine controller system as part of a proof of exception freeness. This illustrates how automated testing can be effectively integrated into a formal safety‐critical process to reduce costs and add value. Copyright © 2000 John Wiley & Sons, Ltd.     

Top-Down Layout for Hierarchical Custom Design

Champ, a chip floor-plan program, and Alpha, an automatic cell placement and routing system, provide a method for hierarchical custom VLSI design that is highly automated and completely top-down. The system can handle standard cell blocks as well as macro cells such as RAMs, ROMs, PLAs. Champ consists of initial block placement and block packing Designers can execute initial block placement either manually or automatically using a method based on attractive-repulsive forces. Block packing is performed automatically or interactively through the moving and reshaping of blocks, which is done as the chip boundaries are being shrunk. Following the floor-plan design, Alpha automatically executes cell placement and routing. Using Champ/Alpha, only seven mandays are needed to design a 20,000-gate VLSI layout, using a predesigned standard cell library and predesigned macro cells.     

Effective Memetic Algorithms for VLSI design = Genetic Algorithms + local search + multi-level clustering

Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35% for the VLSI circuit partitioning problem and 54% for the VLSI standard cell placement problem.     

Quality control of asphalt compaction using GPS-based systemarchitecture

This paper describes research to develop a GPS-based automated quality control system for tracking pavement compaction. The research team has experimented with both vector and raster based algorithms and believe that the raster-based algorithm may be more efficient in this application. Simulated tests on CTS-111 have been extremely encouraging, and the team continues to improve the system for testing. After the tests are completed, the researchers are confident that this technology can be fitted in existing compactors at a cost of about $10,000 per compactor, including GPS devices, radios, hardware, and software