Acoustoelectric interactions in acoustic-surface-wave devices

The principles of a wide range of acoustic-surface-wave devices employing acoustoelectric interactions with semiconductors are described. It is shown that acoustoelectric amplifiers can increase the dynamic range of a delay-line filter. Such devices have been operated on a CW basis and are beginning to become practical. The acoustic convolver and its derivative devices, the optical scanner, the acoustic focusing and imaging devices, and the storage correlator are described. Several of the signal processing applications of the convolver are discussed. Various types of constructional techniques, including the air gap convolver and acoustoelectric amplifier, the strip coupled and external diode convolvers, the use of piezoelectric semiconductors, deposition of a semiconductor on a piezoelectric substrate, and deposition of a piezoelectric material on a semiconducting substrate are discussed.     

Spread Spectrum Receiver Using Surface Acoustic Wave Technology

In this paper, various potential implementations of spread spectrum systems using surface acoustic wave (SAW) devices are discussed and experimental results for a phase-shift keyed (PSK) signal embedded in unwanted interference is presented. An overview of acoustic surface wave technology as it applies to signal processing in spread spectrum communication systems is presented. The ability to implement most of the basic elements of such systems using SAW devices is discussed, with emphasis on the space charge coupled convolver and Fourier transformer. SAW implementation of a fairly general block diagram applicable to a variety of signal and interference situations is described, and the relative advantages of SAW technology with respect to other technologies such as charge coupled devices is discussed.     

Reconfigurable pipelined 2-D convolvers for fast digital signalprocessing

In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset. In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed. In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated. However, the proposed concept is not limited to a particular processor     

Cascadable one/two-dimensional digital convolver

An architecture and a design for a high-speed CMOS digital convolver which can be used for real-time one-dimensional (1-D) and two-dimensional (2-D) signal processing are presented. In the 2-D mode this device can be used to convolve 10-bit image data with a 3×3 or 2×5 2-D eight-bit-per-coefficient impulse response at 20 M samples/s throughput. In 1-D applications it can be used as a ten-tap finite-impulse response (FIR) filter. Devices can be cascaded to increase the order of the convolution reference in both dimensions     

New adaptive-signal-processing concept

A new device is proposed that combines a surface-wave memory with an acoustoelectric convolver to yield an adaptive real-time correlator and convolver. The principal difficulty in combining these devices is obtaining short intense electron bursts in a small gap between a piezoelectric and a semiconductor.     

Multirate-based fast parallel algorithms for DCT-kernel-based real-valued discrete Gabor transform

Fast parallel algorithms for the DCT-kernel-based real-valued discrete Gabor transform (RDGT) and its inverse transform are presented based on multirate signal processing. An analysis convolver bank is designed for the RDGT and a synthesis convolver bank is designed for its inverse transform. The parallel channels in each of the two convolver banks have a unified structure and can apply the fast DCT algorithms to reduce computation. The computational complexity of each parallel channel is low and depends mainly on the length of the discrete input signal and the number of the Gabor frequency sampling points. Every parallel channel corresponds to one RDGT coefficient, and all the RDGT coefficients are computed in parallel during the analysis process and are finally reconstructed in parallel as pieces of the original signal during the synthesis process. The computational complexity related to the computational time of each RDGT coefficient or each piece of the reconstructed signal in the proposed parallel algorithms is analyzed and compared with those in the existing major parallel algorithms for the RDGT and its inverse transform. The results indicate that the proposed multirate-based fast parallel algorithms for the RDGT are attractive for real-time signal processing.     

Fibre-optic multichannel correlation/convolution

A fibre-optic multichannel correlator/convolver based on a two-dimensional systolic array architecture is described. Experimental verification of processor performance is presented.     

单片式西沙瓦波卷积器的研制

单片式西沙瓦波(Seza wa)卷积器是信号处理的重要器件。本文对西沙瓦波卷积器的基本原理、主要设计参数作了描述,给出了我所研制的西沙瓦波卷积器的测试结果,并对器件的性能改进作了讨论。     

Acoustoelectric Convolver Technology for Spread-Spectrum Communications

Acoustoelectric (AE) convolvers for spread-spectrum communication applications are described with input bandwidth capacities to 200 MHz. These devices offer a unique combination of large processing gain, high dynamic range, small size and weight, and low drive power requirements. The programmable feature of convolvers allows the encoding waveform to be changed from bit-to-bit, thereby providing resistance to repeat jamming and enabling secure communications. The basic concepts of a convolver-based spread-spectrum communications system are reviewed, current convolver capabilities are discussed, and projections are made for future device performance. Deviations from nonideal convolver performance are considered. Special techniques which must be used in the system implementation and evaluation of convolvers are described, and the performance level achieved in a state-of-art convolver subsystem is given.     

Monolithic waveguide zinc-oxide-on-silicon convolver

A monolithic waveguide zinc-oxide-on-silicon convolver has been constructed and operated at a centre frequency of 125 MHz. The zinc oxide is originally deposited over the whole substrate and then etched to form the waveguide. The waveguide width is 1/10 of the beam width at the input transducers, which should yield a 20 dB improvement in efficiency over a normal convolver with a beam width equal to the transducer width, after accounting for the loss in the input tapers. Such an improvement was observed in experimental devices.     

Asynchronous operation of an analog convolver

A surface-acoustic-wave convolver can correlate a signal waveform by using an appropriate reference only if the signal arrives within a small time range related to the propagation delay in the device. It is shown here that the complete correlation function can be obtained for arbitrary signal timing if the reference waveform is made repetitive.     

A technique for the design of systolic arrays with bit-level pipelining

This paper describes a method for designing systolic structures with bit-level pipelining. The proposed technique starts with the signal flow graph representation of a given algorithm. A new signal flow graph rule, called the gain transfer rule is introduced to achieve bit-level pipelining. Using this approach, systolic arrays with bit-level pipelining are derived for a general recursive digital filter and a convolver. The proposed technique is quite general and has also been applied to obtain systolic structures for other problems such as vector transformation. In comparison with some previously reported designs, the new architectures are characterized by simpler basic processing cells and faster data throughput rate or smaller chip area requirements.The work of the first two authors was supported by an NRC Resident Research Associateship.     

Processing gain of surface-acoustic-wave convolver with noise-corrupted reference waveform

An analysis is given for the output signal/noise ratio of a convolver when both input waveforms are accompanied by noise. It is shown that a close approximation to the ideal matched-filter performance can be obtained if the signal/noise ratio at the reference input is only 10 dB. Experimental measurements support the analysis.     

Architectures and design techniques for real-time image-processing IC's

A set of eight chips that perform real-time image-processing tasks was designed and fabricated with a 4-/spl mu/m NMOS technology. The chips include a 3/spl times/3 linear convolver, a 3/spl times/3 sorting filter, a 7/spl times/7 logical convolver, a contour tracer, a feature extractor, a lookup-table ROM, and two postprocessors for the linear convolver. All chips were designed with architectures that are dedicated to the particular image-processing task to be performed. The image-processing circuits operate on 10-MHz video data (512/spl times/512-pixel images). The design time for the chips was kept to 1.5 man-years by reusing hardware and using (and developing) appropriate CAD tools, ROM generators and a data-path generator were developed to reduce the circuit design time. An image recognition system was built with these custom chips that can recognize two-dimensional objects that are characterized by their closed outer contours. The complete system is controlled by a Sun workstation and operates at rates up to 15 frames/s. The recognition system achieved a 98% recognition rate for eight objects over a wide range of orientation and size variations and a 100% recognition rate without size variations.     

声表面波卷积器／存储相关器用ZnO膜的制备

本文介绍了声表面波(SAW)卷积器/存储相关器用优质氧化锌(ZnO)压电膜的制备方法。用平面磁控溅射技术溅射ZnO陶瓷靶沉积出了激励SAW西沙瓦模式的优质ZnO膜。用同轴磁控溅射技术溅射ZnO陶瓷靶沉积出的优质ZnO膜制作ZnO/Si单片式SAW卷积器,使该器件性能进一步改善,同时给出了相应的实验结果。     

Two-dimensional high-speed acoustic Fourier transform of optical images

We employ a two-dimensional (2D) semiconductor acoustic convolver to generate the Fourier transform of 2D images. The transformed plane is raster-scanned along oblique lines with variable tilt angle, and the line time can vary from a few microseconds upwards.     

Ambiguity-function generator using acoustic surface-wave convolvers

It is shown that ambisuity function of a time-limited signal can be obtained using ultrasonic convolvers. Experimental results are presented using a separate media space charge coupled acoustic surface-wave convolver.     

Adaptive noise cancellation with a SAW storage correlator

A Sezawa wave storage correlator was used to implement an adaptive filter for noise cancellation. The filter reduced the level of a 150 MHz CW jamming signal by 26 dB and a broadband Sezawa wave convolver was used to compress an underlying chirp signal. The tap weights are determined in 40 to 100 ?s, depending on the jamming signal power and feedback gain.     

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

A 200-MHz 16-b BiCMOS super high-speed signal processing (SSSP) circuit has been developed for high-speed digital signal processor (DSP) LSIs. In order to produce extremely fast LSI circuits, several novel techniques have been combined for integration of the SSSP. They include a redundant binary convolver architecture, a double-stage pipelined convolver architecture, and submicrometer BiCMOS drivers with large capacitive load drivability. The SSSP performs 200-MHz addition. The chip, which was fabricated with 0.8-μm BiCMOS and triple-layer metallization technology, has an area of 5.87 mm×5.74 mm and contains 20150 transistors. It operates at a clock frequency of 200 MHz with a single 5-V power supply and typically consumes 800 mW     

An integrated piezoelectric-insulator DMOST surface-acoustic-wave convolver

A detailed investigation and analysis of a new device, the PI-DMOST convolver, is presented. The feasibility of this type of convolver has been previously demonstrated [1]. In this paper, we present the experimental results of another configuration of the device, fabricated with a new process. The theory is presented in detail for operation of the convolver using first-order Rayleigh-mode waves, and then extended to include other SAW modes.The convolver measures 100 μm by 1 cm, has a dynamic range of 70 dB, and is realized using ZnO piezoelectric films on a planar-processed silicon wafer.