A methodology for efficient hardware verification

We present a methodology which helps structure the design and verification of hardware circuits. Our methodology supports reusable proofs of hardware components, provides for multiple implementations of the same specification, and allows both bottom up and top down verification styles. We provide mechanical assistance for our methodology in the Nuprl proof development system. Our method exploits Nuprl's rich type theory to encode the specification of a module in the type of the module. This allows us to elegantly describe parameterized hardware modules. The methodology is efficient because: the automated support reduces the amount of information that users must provide and the use of parameterized hardware modules eliminates redundant reasoning among proofs of hardware components. In this paper we explain our methodology and illustrate our approach with several examples of circuit verification.     

Building a real-time kernel: First steps in validating a pure process/ADT model

A model based on simple, unadorned processes and abstract data types has been proposed for the design and implementation of real-time systems. We describe our generally successful experiences in using this model for the construction of a real-time operating system kernel containing services for process control, synchronization, time and input-output. Our work and results focus on the usefulness of the scheme for designing modules at hardware/software interfaces, for predicting deterministic timing behaviour, and for software development.     

基于语义与句法的Java类库检索方法与系统

提出了一个支持系统化、大规模软件复用的基于语义与句法的可复用模块的检索方法，并介绍了基于此方法支持Jwa类库的实用检索系统。软件开发者既可以使用自然语言直接描述待开发软件的功能语义并用此查询类库中的相关模块，也可以通过对输入输出数据类型的描述对Java类库进行快速地查询，还可以同时使用两者的组合来提高可复用库模块查询的精度。     

基于去噪技术的DSP语音识别系统设计

针对语音识别系统对抗环境噪声的实际需求,提出一种二次组合抗噪技术,研究并设计了一种以数字信号处理器(DSP)为硬件平台,以隐马尔可夫模型(HMM)为算法的抗噪声嵌入式语音识别系统.DSP采用型号为TMS320VC5509A的芯片,配以外围硬件电路构成语音识别系统的硬件平台.软件设计以离散隐马尔可夫模型(DHMM)为识别算法进行编程,系统软件主要有识别、训练、学习和USB四个主要模块.实验结果表明:基于二次组合去噪技术的语音识别系统有更好的抗噪声效果.     

Design of real-time periodic control systems through synchronization and fixed priorities

Control systems are often designed using a set of co-operating periodic modules running under control of a real-time operating system. A correct behaviour of the closed-loop controller requires that the system meets timing constraints like periods and latencies, which can be expressed as deadlines. The control system timing requirements are captured through a partition in control paths by which priorities are assigned according to their relative urgency. Latencies are managed through precedence constraints and more or less tight synchronization between modules. The implementation uses the fixed-priority based pre-emption service of an off-the-shelf real-time operating system. Such a system can be modelled with timed event graphs, and its temporal behaviour can be analysed using the underlying (max, plus) algebra. Examples coming from a uni-processor robot controller are provided.     

矩阵式LED远光灯智能辅助控制系统

针对现有汽车远光灯需要司机通过自身对路况的判断来完成手动操作，从而可能造成行车时因违规使用车灯而发生交通事故的问题，完成了基于不同路况和周围环境自动调节远光灯照射方式的矩阵式LED远光灯智能辅助控制系统的设计与实现。首先，根据车辆行驶特点及相关交通法规，针对不同的车前路况，提出矩阵式LED远光灯辅助系统的智能控制策略；然后，对系统的软硬件进行设计与实现，硬件部分主要包括主控制器模块、LED电源驱动模块以及矩阵开关控制模块的选型与电路设计，软件部分主要包括驱动电路控制、矩阵开关控制以及智能控制策略等功能模块；最后，在实验室环境下通过搭建完整的实验系统进行了功能测试。实验测试结果表明，所提方法控制结果准确、实时性好、可靠性高、易于实现，达到了预期目标。     

汽车记录仪数据采集系统的设计

从硬软件的角度研究了基于 S3C2410的汽车记录仪数据采集系统的设计,对采集系统中三大主要模块即:实时时钟信号模块、车速采集模块、开关量模块分别进行了研讨,经过实验证明,将此采集系统应用于汽车记录仪中,该采集系统采集精度高,抗干扰性强,性能可靠,价格低廉,具有很好的应用前景和较高的通用性与实用性。     

基于FPGA的GPS同步授时与守时方案设计与实现

针对电力系统异地实时同步测量中时间同步的问题,设计并实现了一种基于FPGA的电力系统GPS同步授时与守时方案.运用了平均值减小误差的思想,给出了方案的总体硬件设计以及芯片选型,重点介绍了FPGA内部功能模块设计,主要包括初值计算模块、平均值计算模块、平均值记录模块和PPS(秒脉冲)生成模块等,使用VHDL对各模块进行软件设计并提供了设计思路.通过硬件实验验证,无论卫星是否失锁,都能保证GPS长时间的高精度授时.     

Modular architecture for custom-built systems oriented to real-time computer vision: Application to color recognition

This paper presents a modular architecture called DIPSA, which is intended to be used for building custom-made real-time Computer-Vision systems. It consists of four module types and each of them represents a family of circuits that perform specific visual tasks. Our architectural model proposes an algorithm-dependent methodology and makes good results possible using problem oriented solutions. The desired performance is achieved choosing the appropriate modules and connecting them by means of heterogeneous pipeline and concurrence. Additionally, two DIPSA-based hardware systems for real-time Color Recognition are described here.     

A learning-based module extraction method for object-oriented systems

Developers apply object-oriented (OO) design principles to produce modular, reusable software. Therefore, service-specific groups of related software classes called modules arise in OO systems. Extracting the modules is critical for better software comprehension, efficient architecture recovery, determination of service candidates to migrate legacy software to a service-oriented architecture, and transportation of such services to cloud-based distributed systems. In this study, we propose a novel approach to automatic module extraction to identify services in OO software systems. In our approach, first we create a weighted and directed graph of the software system in which vertices and edges represent the classes and their relations, respectively. Then, we apply a clustering algorithm over the graph to extract the modules. We calculate the weight of an edge by considering its probability of being within a module or between modules. To estimate these positional probabilities, we propose a machine-learning-based classification system that we train with data gathered from a real-world OO reference system. We have implemented an automatic module extraction tool and evaluated the proposed approach on several open-source and industrial projects. The experimental results show that the proposed approach generates highly accurate decompositions that are close to authoritative module structures and outperforms existing methods.     

基于uCOS-II的嵌入式数控系统实时性分析

提出了一种嵌入式数控系统的软硬件体系结构，该系统采用实时操作系统uCOS-II和ARM嵌入式微处理器构建。结合实时多任务操作系统的性能指标，分析了嵌入式实时操作系统uCOS-II的时间特性，并给出了uCOS-II中最长时间特性的计算方法，同时，在数控系统的平台上，测试了系统任务调度各个阶段所用时间，并对此系统的实时性和稳定性进行了分析。结果表明，基于uCOS-II和ARM所构建的嵌入式数控系统的实时性好，且具有低成本、高性能的特点，具有广泛的应用前景。     

The programmable network prototyping system

The programmable network prototyping system (PNPS) uses a collection of reusable hardware modules that implement generic communications functions such as transmission, reception, signal propagation, and pattern matching. These modules are interconnected and configured to emulate a variety of communication networks whose behavior can be monitored under different load conditions. The user specifies a network as a set of interacting components using available software tools. These tools are accessible within a prototyping environment that includes a control system for configuring the hardware modules and interconnecting them according to the component specifications. Previously designed components are stored in a library and can be used to specify new networks. Although PNPS is designed to provide a prototyping environment for communication networks, some of the basic ideas can be useful in other contexts     

Synthesis of hierarchical systems

In automated synthesis, given a specification, we automatically create a system that is guaranteed to satisfy the specification. In the classical temporal synthesis algorithms, one usually creates a “flat” system “from scratch”. However, real-life software and hardware systems are usually created using preexisting libraries of reusable components, and are not “flat” since repeated sub-systems are described only once.In this work we describe an algorithm for the synthesis of a hierarchical system from a library of hierarchical components, which follows the “bottom-up” approach to system design. Our algorithm works by synthesizing in many rounds, when at each round the system designer provides the specification of the currently desired module, which is then automatically synthesized using the initial library and the previously constructed modules. To ensure that the synthesized module actually takes advantage of the available high-level modules, we guide the algorithm by enforcing certain modularity criteria.We show that the synthesis of a hierarchical system from a library of hierarchical components is Exptime-complete for μ-calculus, and 2Exptime-complete for Ltl, both in the cases of complete and incomplete information. Thus, in all cases, it is not harder than the classical synthesis problem (of synthesizing flat systems “from scratch”), even though the synthesized hierarchical system may be exponentially smaller than a flat one.     

实时在线UPS电源监控系统硬件设计与分析

针对UPS电源监控方面存在的不足,设计了实时在线的监控系统。设计了系统的硬件功能模块,给出具体电路原理图;应用Markov理论,对系统的单个硬件功能模块和整个系统进行了可靠性分析与建模;应用所建立的模型,对单个硬件模块的可靠度和系统的可靠度进行了定量计算。通过分析计算,提出的方法具有一定的实用性。     

Design and realization of a high resolution (640 × 480) SWIR image acquisition system

A new image acquisition system module for extracting signals of high-resolution short wave infrared (SWIR) from a focal plane array (FPA) is presented in this study. The short wave infrared (SWIR—with wavelength about 900–1,700 nm) images have been proven its unique values in many applications such as military, semiconductor inspection and aviation security. The designs for the SWIR data acquisition system module consists of digitization and acquisition of FPA signals, design of synchronous dynamic random access memory controller and real-time image signal transformation and display. Three major steps involved towards a successful SWIR module—(1) Selection of hardware ICs according to specification for the FPA; (2) Design of a timing generator for the image acquisition system to control FPA and other ICs by Verilog HDL programming; (3) Integrate the individual modules on a PCB. The SWIR image output signals are successfully generated in the format of National Television System Committee (NSTC), which can be displayed on a common NTSC monitor, flat panel displays with an AV input terminal or a CRT display in a favorable speed of frame rate at 30 per second.     

开放式网络化自动测试系统体系结构研究

研究了开放式网络化自动测试系统的体系结构;在充分考虑开放性、通用性和实时性等要求的基础上,建立了基于C/S和B/S混合结构的开放式网络化自动测试系统硬件模型;以国际标准为基础,研究了开放式网络化自动测试系统的软件体系结构,借鉴Kruchten方法,从框架模型、功能模型、计算模型等多个视角对系统的软件体系结构进行了建模分析;该成果为构建开放式网络化自动测试系统的硬、软件的顶层设计提供参考价值,并有助于确保系统开发的有效性。     

Cathedral-II: A Silicon Compiler for Digital Signal Processing

The article describes the status of work at IMEC on the Cathedral-II silicon compiler. The compiler was developed to synthesize synchronous multiprocessor system chips for digital signal processing. It is a continuation of work on the Cathedral-I operational silicon compiler for bit-serial digital filters. Cathedral-II is based on a ?meet in the middle? design method that encourages a total separation between system design and reusable silicon design. The CAD system includes a rule-based synthesis program, a procedural program, and a controller synthesis environment. Processors are synthesized in terms of modules called from automated reusable module generators. Chip layout is done on a floor planner. An expert subsystem verifies correctness during silicon design and generates functional and timing models for verification at the module and chip levels.     

基于事件驱动的软硬件混合监测系统--嵌入式系统辅助设计新技术

介绍了一种以事件驱动软硬件混合监测系统实现的辅助设计技术,适应于采用IPcore技术、基于平台的嵌入式系统自动化设计。给出了该系统的原理、架构及其重要部分的设计实现,包括事件驱动工作原理、硬件单元的组成、软件单元的各模块及EAT等。该监测系统允许从不同的抽象层面(如系统功能级)精确观察并分析待测系统的行为,为复杂系统的设计提供强有力的支持。     

基于无线传感器网络的氯气监测系统设计

基于433 MHz的无线自组网监测系统,设计了恒电位电解式氯气传感器的信号调理电路、信号采集和处理电路、电源管理模块、人机交互界面,搭建了基于星状拓扑的通信平台。解决了无线模块中电池欠电状态对监测带来盲点的问题,完成了环境中氯气含量的实时监测系统软硬件设计。该系统运行稳定,易于扩展,具有广阔的应用前景。