MCM-C/D微波基板工艺技术研究

提出了一种新型的MCM-C/D微波基板研制方法,克服了低温LTCC基板微带线耐焊性差及附着力差的缺点。研究了MCM-C/D基板的膜层结构特征及制作过程的工艺控制方法,并给出相应的试验结果,这对于微波电路基板的设计和应用有一定的参考价值。     

"集成电路分析与设计"课程的实验教学方法改革

本文以"集成电路分析与设计"课程的一个实验"D触发器设计"为例,介绍一种实验教学方法,帮助学生掌握全定制集成电路设计流程和使用集成电路设计相关EDA软件,达到学生能够独立进行集成电路设计的目的.教学实践证明,该教学方法切实可行,具有良好的教学效果.     

Performance of heterostructure FET's in LSI

This paper reports a comparative evaluation of circuits based on heterostructure field-effect transistors (HFET's) for delay, noise-margin and power dissipation in unloaded and loaded configurations. n-channel enhancement/depletion (E/D) circuits operating at 300 and 77 K and complementary circuits operating at 77 K are compared with respect to each other. The paper also shows that a modified short-channel MOSFET model gives good agreement with experimental behavior of the devices and is adequate for evaluation. Fan-in (FI) sensitivities of delay are much smaller than fan-out (FO) sensitivities of delay for E/D circuits because of capacitive effects. E/D circuit delays are more fan-out sensitive at 300 K than at 77 K because of lower current capability. The fan-in sensitivity of the delay of complementary circuits is larger and is comparable to that circuit's fan-out sensitivity. Under loaded conditions (FI is 3, FO is 3, capacitance is 0.1 pF) at 77 K, 0.5-µm gate length E/D structures show gate delays near 50 ps and 1.0-µm gate length show gate delays near 75 ps. The circuits at 300K exhibit a doubling of the gate delay. The complementary circuits offer, at 77 K, a performance of 70 ps at 0.5-µm gate length and 140 ps at 1.0-µm gate length. The significant performance improvements of complementary circuits with reduction of gate lengths to submicrometer dimensions occurs primarily due to reduction in the device capacitances and secondarily due to improvement of current characteristics. They demonstrate noise margins that are more than 50 percent better than their E/D counterpart along with lower power dissipations. The larger noise margin may be a significant advantage because the small logic swings require stringent parasitic resistance and threshold voltage control.     

基于翻转信息熵的组合逻辑电路功耗分析

基于信息熵的复杂度分析方法是在VLSI设计流程的高层次抽象阶段对组合逻辑电路功耗和面积进行分析估计的可行方法之一.本文通过提出新的利用翻转信息熵进行电路实现面积和功耗估计的理论方法,改善了面积和功耗估计精度.大量基于随机电路和BENCHMARK电路的实验结果表明,上述方法能够使面积和功耗估计的相对误差分别降低24.3% (从12.74%到9.65%)和15.4% (从13.67%到11.57%).     

Power-Conditioning Circuitry for a Self-Powered System Based on Micro PZT Generators in a 0.13-$muhbox{m}$ Low-Voltage Low-Power Technology

The concept and design of a power-conditioning circuit for an autonomous low-power System-in-Package (SiP) is presented in this paper. The SiP's main power source is based on the use of micropiezoelectric generators. The electrical model of the power source, which has been obtained based on experimental measurements and implemented on Cadence Analog Artist's Spectre simulation environment, is explained. The model has been used to simulate the power source with the power-conditioning electronics over the entire design process. Finally, the simulated and experimental results of the developed integrated power circuits, which are formed by a rectifier and a low-power bandgap reference voltage source to define the threshold voltage for the closed-loop regulation process, are also shown. These circuits have been designed using a commercial 0.13-$muhbox{m}$ technology from ST Microelectronics through the Multi-Projects Circuits (CMP) Techniques of Informatics and Microelectronics for Integrated Systems Architecture (TIMA) service.      

GaAs DCFL超高速集成电路研究

直接耦合场效应逻辑（ＤＣＦＬ）具有简单的结构、良好的速度／功耗性能，是ＧａＡｓＦＥＴＬＳＩ电路中一种重要的逻辑形式。传统Ｅ／Ｄ型ＤＣＦＬ电路具有较低的成品率和较差的温度特性，本文研究了改进的Ｅ／Ｅ型ＤＣＦＬ电路。对Ｅ／Ｄ、Ｅ／Ｅ型ＤＣＦＬ电路的直流、瞬态及温度特性进行了分析、模拟和比较，Ｅ／Ｅ逻辑具有良好的高温性能。经优化设计，最后制作出单门延迟约１００ｐｓ、单门功耗约１ｍＷ的Ｅ／Ｄ和Ｅ／Ｅ型ＤＣＦＬ电路，且Ｅ／Ｅ型电路较Ｅ／Ｄ型电路具有更高的成品率。     

Equalization of Waveguide Delay Distortion

Microwave all-pass circuits, consisting of reactive networks used in conjunction with wide-band circulators or couplers, are described. An extremely useful all-pass circuit for minimizing phase distortion results when the restive network is a linear taper extending beyond cutoff. The delay characteristics of this circuit are well suited to the correction of the dispersive characteristics of TE or TM mode waveguides. Design formulas have been derived for the parameters of the tapers and a set of design curves is presented. The use of composite tapered sections and the use of tapers in conjunction with other equalizing circuits are described. Experimental results have been obtained for the phase of the reflection factor of a linear taper. Close agreement was observed between the results predicted by theory and the experimental data. Typical examples demonstrate that the time-delay variation of a length of uniform waveguide can be substantially reduced by linearly tapered waveguide equalizers.     

A 6.5-ns GaAs 20×20-b parallel multiplier with 67-ps gatedelay

The performance and yield of LSI circuits have been characterized over a wide variation in processing parameters and power supply voltage, and over the military temperature range using 4×4-, 8×8-, 12×12-, 16×16-, and 20×20-b multipliers. These parallel array multipliers with carry-save adder architecture have been implemented in low-power GaAs enhancement/depletion (E/D) direct-coupled FET logic (DCFL). The circuits were fabricated with a multifunction self-aligned gate process, which features a buried p-layer for high yield and manufacturability. Worst-case multiplication times ranging from 870 ps (51 ps/gate) for the 4×4-b, to 6.48 ns (67 ps/ gate) for the 20×20-b multiplier were obtained, with the fastest extracted gate delays yet reported for LSI circuits. The 20×20-b multiplier, with 18573 active devices (4902 logic gates), shows a wafer-probe yield as high as 61% on the best-yielding wafers. It is concluded that the E/D DCFL family is capable of providing LSI circuits operating over a wide variation in power-supply voltage and over the full military temperature range     

通用型高功率因数高频开关电源的开发

本文主要针对国内高频电源市场发展的现状,对电源的小型化设计、分布式模块化设计、功率因子改善和高次谐波抑制等问题进行了探讨,介绍的是一种通用型高功率因数高频开关电源产品的开发.设计中变换器采用推挽-正激DC-DC变换器拓扑形式,控制芯片的设计主要包括PFC、PWM两个环节的电路设计及相关外部电路的构建.整个系统采用模块化设计,各模块间的均流采用最大电流法自动均流技术实现.设计的各项指标在试验中均达到预期要求,进一步完善后即可投入市场使用.     

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $Sigma Delta$ Modulator

Although SigmaDelta modulators have largely been implemented as discrete-time (DT) circuits, a continuous-time (CT) approach offers significant advantages for realizing high-accuracy A/D converters at signal bandwidths where technology considerations may impose significant constraints. A CT design allows for relaxed amplifier unity-gain frequency and power requirements, which can enable the realization of high-resolution modulators with bandwidths of several MHz or more at low power. It also provides the advantage of inherent anti-aliasing filtering. This paper introduces a hybrid CT/DT SigmaDelta modulator for A/D conversion that combines the benefits of CT and DT circuits, while mitigating the challenges associated with CT design. The second-order first stage of a two-stage cascade is implemented in CT, while the first-order second stage is a DT circuit. An experimental prototype of the proposed modulator, integrated in 0.18-mum CMOS technology, operates from a 1.2-V analog supply to allow for easier migration to a 0.13-mum or 90-nm CMOS technology. The prototype achieves a dynamic range of 77 dB, a peak SNR of 71 dB, a peak SNDR of 67 dB, and worst-case anti-aliasing filtering of 48 dB for a signal bandwidth of 7.5 MHz and a sampling rate of 240 MHz. The total power dissipation is 89 mW, including 63.6 mW of analog power.     

GaAs MOSFET High-Speed Logic

Enhancement-mode GaAs MOSFET integrated logic shows superior potential for applications in low-power high-speed integrated circuits. The speed / power performance of this logic was investigated by using GaAs MOSFET ring oscillators, fabricated using a low-temperature plasma oxidation technique for gate insulation. With an enhancement-depletion (E/D)-type ring oscillator, a minimum propagation delay of 110 ps per gate is obtained, with a power/speed product of 2.0 pJ. With an enhancement-enhancement (E/E) type, a minimum power/speed product of 26 fJ is obtained, with a 385-ps delay. These performances are equal to or better than those of GaAs MESFET logic, after adjustments are made for gate size. With further refinements in device geometry and improvements in gate oxide, GaAs MOSFET logic will be of great use in high-speed very-large-scale integrated circuits.     

Large signal design of broadband monolithic microwave frequencydividers and phase-locked oscillators

This paper presents a design method for phaselocked devices such as frequency dividers or injection-locked oscillators. The method requires a full nonlinear analysis of the circuit. This analysis relies upon harmonic balance techniques and is suitable for monolithic circuits simulation. First, a modified formulation of the general harmonic balance equation is proposed which includes the presence of probes. These probes allow us to suppress the degenerated solution of the HB equation in autonomous cases. Moreover, a global stability analysis of phaselocked regimes is carried out. It provides invaluable information on the nonlinear behavior of the device. In particular, synchronization bandwidths as well as power ranges for which the circuit can be synchronized are obtained from the stability loci drawn in the parameter space. All these features have been used to design a broadband monolithic frequency divider, and the simulated and experimental results have been compared with very good accuracy. Therefore, the method proposed is a very useful tool for the design of potentially unstable circuits     

基于传输电流开关理论的电流型CMOS ADC电路设计

本文利用数字电路设计理论中的舆电流开关理论对Ａ／Ｄ转换器的转换过程进行了分析,提出了仅基于该理论的电流型ＣＭＯＳ Ａ／Ｄ转换器电路设计。与传统的Ａ／Ｄ转换器电路设计比较,它避免了复杂的模拟信号处理部分电路,显著地简化了电路结构。结果表明该电路设计具有正确的逻辑功能。     

A Simple Method for Millimeter-Wave Finline Balanced Mixer Design Using Three-Dimensional Field Simulation Software

In this paper, a simple method for millimeter-wave finline balanced mixer design using three-dimensional field simulation software has been proposed. The method can be widely used to design the diode-based circuits, especially for the circuit structures with orthogonal field in some specific hybrid integrated circuits which are unavailable to be designed using the circuit simulator. In these circuits, the power directly at diodes is correlated to the input reflection coefficient. The diodes mounted on the finline circuits are defined as impedance boundary in the commercial computer-aided design (CAD) tool High Frequency Structure Simulator (HFSS) model, and hence simulation with the use of HFSS can be implemented to optimize the input matching network of the finline circuits for transferring maximum power to the diodes. Two finline balanced mixers at U-band using commercial GaAs Schottky diodes have been designed and fabricated to validate this method. Matching structures at the radio frequency (RF) port have been employed for a better return loss and a lower conversion loss. Experiment results are presented and show good agreement with simulation data. The proposed method has proven to be useful for the design of millimeter-wave mixers in finline technique.     

1μm栅HEMT DCFL门电路及环形振荡器的设计与实验研究

利用作者提出的HEMT DCFL倒相器直流传输特性及瞬态特性计算机分析的模型,设计并制成了HEMT DCFL门电路及环形振荡器.在电路设计中,重点讨论了E/D NEMT倒相器的电路性能与器件的主要参数(栅长、栅宽、阈压)间的理论关系.工艺研究中,建立了挖栅时沟道饱和电流Is′与阈压值V_(t~h)间关系的理论曲线,并改进了传统化学湿法刻蚀工艺的阈压均匀性及E,D器件电流匹配的控制精度.实验制作了栅长为1μm的增强型和耗尽型HEMT.在1×1mm范围内,阈压偏差小于50mV,E/D倒相器的传输特性为:V_(OH)≈V_(DD),V_(OL)<0.1V,高、低电平转换范围仅0.1V,噪容达0.3V左右.研制的9级、17级环形振荡器,在V_(DD)为0.5V到3.5V范围内都观察到正弦波振荡波形.     

基于PC机的电机控制教学实验装置的研制

本文简要介绍了为配合电机控制课程教学而设计制作的、基于Pc机的电同闭环调速系统实验装置。以数字化、集成化为设计原则，系统采用PC机与外部控制电路相结合的数字PI控制方式，将计算机强大的数字处理能力和图形处理能力应用于电机双闭环调速。针对交壹流电机设计了4个典型实验的外部控制电路，采用PC机集中控制，通过一套AD／DA转换与PC机进行数据交换和指令传送，充分利用资源。文中介绍了该装置的软硬件设计思路和要点，给出了应用实例。     

Feasibility and performance region modeling of analog and digital circuits

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is general and is applicable to both analog and digital circuits. This feature makes it particularly suitable for mixed-signal designs.This research was supported in part by a grant from NSF (MIP-9110719)     

功率因数提高的教学探讨和实践

以功率因数的提高为例，将正弦稳态电路的理论教学与工业应用相结合，在课堂教学中进行了多角度阐述的多元化教学的实践，同时在实验教学中鼓励学生自己设计电路，进行实验对比分析，在实验结果出现问题时，结合功率因数提高在电力系统中的实际工业应用，让学生再次设计和分析电路并进行实验，使理论教学和实验教学有效地结合，加强了正弦稳态电路理论的教学，取得了满意的教学效果。     

Dynamic GaAs capacitively coupled domino logic (CCDL)

Dynamic capacitively coupled domino logic (CCDL) has been proposed as a practical means of implementing low-power and high-speed complex gates. The CCDL gate delay characteristics obtained from an analytical model and from test circuits implemented in a 1-μm GaAs E/D process are presented. In addition, the feasibility of using CCDL gates to implement practical circuits is demonstrated by the experimental characterization of a 4-b carry-lookahead adder. The adder has a critical delay of 1.1 ns and a power dissipation of 96 mW. A comparison of the dynamic CCDL adder with conventional static designs indicates the advantages of dynamic CCDL gates in reducing power dissipation and increasing speed, making such gates suitable for VLSI implementations     

Compensation-circuit to improve radiation-hardness in GaAsdigital-circuits, based on X-ray studies

Earlier results have shown that GaAs devices do not exhibit appreciable degradation up to a radiation dose of nearly 10⁸ rad (GaAs). The results of this work suggest that GaAs devices and circuits are sensitive to radiation exposure at dose levels below 10⁸ rad(GaAs). Degradation was observed in E-MESFET and D-MESFET parameters and in circuit performance for devices which were designed and fabricated in a 1.2 μm GaAs process, when exposed to varying doses of 1.49 keV X-rays in the range 40-65 Mrad (GaAs). The degradation is attributed to the change in the properties of the MESFET channel region, caused by the transport of the atomic hydrogen from the passivation layer to the channel. A compensation circuit, based on the observed behavior of radiation effects on GaAs devices, has been designed to improve the radiation insensitivity of GaAs (E/D) based circuits under SPICE (Simulation Program with IC Emphasis) simulated conditions. Its usefulness is demonstrated through a DCFL inverter circuit up to nearly 10⁸ rad (GaAs) dose level. The results of this work can be used in the design of complex-function radiation-insensitive DCFL based circuits