Plasmonic‐Radiation‐Enhanced Metal Oxide Nanowire Heterojunctions for Controllable Multilevel Memory

Nanowire memristor devices that display multilevel memory effects are of great interest for high‐density storage, however, numerous challenges remain in fabricating high‐quality, stable memory units. A plasmonic‐radiation‐enhanced technique is introduced in this work for scalably forming nanowire multilevel memory units with superior properties. Femtosecond laser irradiation of gold‐titanium dioxide nanowire‐gold structures results in plasmonic‐enhanced optical absorption in the TiO₂ locally at the metal‐oxide interface. This produces junctions with superior mechanical and electrical contact, and engineers a concentration of charged defects in the TiO₂ near the interface, which enables stable multilevel memory behavior without the need for a traditional electroforming step. The memory units produced display eight‐level current amplification under continuous forward voltage cycles, and can replicate complex multilevel memory sequences without interference between the different multilevel states.     

Memristive Logic‐in‐Memory Integrated Circuits for Energy‐Efficient Flexible Electronics

A memristive nonvolatile logic‐in‐memory circuit can provide a novel energy‐efficient computing architecture for battery‐powered flexible electronics. However, the cell‐to‐cell interference existing in the memristor crossbar array impedes both the reading process and parallel computing. Here, it is demonstrated that integration of an amorphous In‐Zn‐Sn‐O (a‐IZTO) semiconductor‐based selector (1S) device and a poly(1,3,5‐trivinyl‐1,3,5‐trimethyl cyclotrisiloxane) (pV3D3)‐based memristor (1M) on a flexible substrate can overcome these problems. The developed a‐IZTO‐based selector device, having a Pd/a‐IZTO/Pd structure, exhibits nonlinear current–voltage (I–V) characteristics with outstanding stability against electrical and mechanical stresses. Its underlying conduction mechanism is systematically determined via the temperature‐dependent I–V characteristics. The flexible one‐selector?one‐memristor (1S–1M) array exhibits reliable electrical characteristics and significant leakage current suppression. Furthermore, single‐instruction multiple‐data (SIMD), the foundation of parallel computing, is successfully implemented by performing NOT and NOR gates over multiple rows within the 1S–1M array. The results presented here will pave the way for development of a flexible nonvolatile logic‐in‐memory circuit for energy‐efficient flexible electronics.     

Memristor based N-bits redundant binary adder

This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU. New possible solutions for multi-level logic designs can be established by utilizing the memristor dynamics as a basis in the circuit realization. The proposed memristor-based redundant binary adder circuit tries to achieve the theoretical advantages of the redundant binary system, and to eliminate the carry (borrow) propagation using signed digit representation. The advantage of carry elimination in the addition process is that it makes the speed independent of the operands length which speeds up all arithmetic operations. One memristor is sufficient for both the addition process and for storing the final result as a memory cell. The adder operation has been validated via different cases for 1-bit and 3-bits addition using HP memristor model and PSPICE simulation results.     

Hybrid crossbar architecture for a memristor based cache

This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 3 times the bit density of an STT-MRAM system and up to 11 times the bit density of an SRAM architecture. The proposed architecture is analyzed using a detailed SPICE analysis that accounts for the resistance of the wires in the memristor structure. Additionally, the memristor model used in this work has been matched to specific device characterization data to provide accurate results in terms of energy, area, and timing. The proposed memory system was analyzed by modeling two different devices that vary in resistance range and switching time. This system does not require that the memristor devices have inherent diode effects which limit alternate current paths. Therefore this system is capable of utilizing a much broader class of devices.An architectural analysis has also been completed that shows how the memory system may perform as a cache memory. A hybrid cache structure was used to alleviate the long write latencies of memristor devices. This approach consisted of the tag array being made of SRAM cells while the data array was made of the memristor circuit proposed. This hybrid scheme allows multiple reads and writes to concurrently access different sub-arrays within a cache. The performance of these novel memristor based caches was compared to SRAM and STT-MRAM based caches through detailed simulations. The results show that the memristor caches are denser and allow better performance along with lower system power when compared to the STT-MRAM and SRAM caches.     

A double-level-Vth select gate array architecture formultilevel NAND flash memories

In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, “A double-level-V_th select gate array architecture” to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized     

Truly Electroforming‐Free and Low‐Energy Memristors with Preconditioned Conductive Tunneling Paths

1S1R (1 selector and 1 memristor) is a laterally scalable and vertically stackable scheme that can lead to the ultimate memristor density for either memory or neural network applications. In such a scheme, the memristor device needs to be truly electroforming‐free and operated at both low currents and low voltages in order to be compatible with a two‐terminal selector. In this work, a new type of memristor with a preconditioned tunneling conductive path is developed to achieve the required performance characteristics, including truly electroforming‐free, low current below 30 µA (potentially <1 µA), and simultaneously low voltage ≈±0.7 V in switching operations. Such memristors are further integrated with two types of recently developed selectors to demonstrate the feasibility of 1S1R integration.     

Comparative analysis of memristor models and memories design

The advent of the memristor breaks the scaling limitations of MOS technology and prevails over emerging semiconductor devices.In this paper,various memristor models including behaviour,spice,and experimental are investigated and compared with the memristor's characteristic equations and fingerprints.It has brought to light that most memristor models need a window function to resolve boundary conditions.Various challenges of availed window functions are discussed with matlab's simulated results.Biolek's window is a most acceptable window function for the memristor,since it limits boundaries growth as well as sticking of states at boundaries.Simmons tunnel model of a memristor is the most accepted model of a memristor till now.The memristor is exploited very frequently in memory designing and became a prominent candidate for futuristic memories.Here,several memory structures utilizing the memristor are discussed.It is seen that a memristor-transistor hybrid memory cell has fast read/write and low power operations.Whereas,a 1T1R structure provides very simple,nanoscale,and non-volatile memory that has capabilities to replace conventional Flash memories.Moreover,the memristor is frequently used in SRAM cell structures to make them have non-volatile memory.This paper contributes various aspects and recent developments in memristor based circuits,which can enhance the ongoing requirements of modem designing criterion.     

基于异构忆阻器的1T2M多值存储交叉阵列设计

忆阻器作为一种新型电子元件,具有尺寸小、读写速度快、非易失性和易于与CMOS电路兼容等特性,是实现非易失性存储器最具发展前景的技术之一。但是已有的多值存储交叉阵列存在电路结构复杂、漏电流和存储密度低等问题,影响了多值存储交叉阵列的实用性。该文提出一种基于异构忆阻器的多值存储交叉阵列,其中存储单元由1个MOS管和两个具有不同阈值电压和R_on阻值的异构忆阻器构成(1T2M),可实现单个电压信号完成4值读写的操作,减少电流通路的同时简化了电路结构。通过PSpice进行仿真验证,表明所提出的1T2M多值存储器交叉阵列与已有工作相比,电路结构更简单,读写速度更快,并较好地克服了漏电流问题。     

忆阻器堆叠交叉阵列漏电流问题研究进展

忆阻器是一种新型的非易失性存储器,具有结构简单、功耗低、集成密度高、类突触性质等特点。忆阻器主要以交叉阵列的形式作为人工突触,被用于构造人工神经网络,然而,忆阻器的交叉阵列面临着潜在的通路漏电流问题,这阻碍了忆阻器的进一步应用。文章简要分析了忆阻器堆叠交叉阵列产生漏电流的原因,主要介绍了二极管-忆阻器、选通器-忆阻器、晶体管-忆阻器等多种抑制漏电流的方案,总结并展望了超大规模集成忆阻器的应用前景。     

A Natural Silk Fibroin Protein‐Based Transparent Bio‐Memristor

The recent discovery of nanoelectronics memristor devices has opened up a new wave of enthusiasm and optimism in revolutionizing electronic circuit design, marking the beginning of new era for the advancement of neuromorphic, high‐density logic and memory applications. Here a highly non‐linear dynamic response of a bio‐memristor is demonstrated using natural silk cocoon fibroin protein of silkworm, Bombyx mori. A film that is transparent across most of the visible spectrum is obtained with the electronic‐grade silk fibroin aqueous solution of ca. 2% (wt/v). Bipolar memristive switching is demonstrated; the switching mechanism is confirmed to be the filamentary switching as observed by probing local conduction behavior at nanoscale using scanning tunneling microscopy. The memristive transition is elucidated by a physical model based on the carrier trapping or detrapping in silk fibroin films and this appears to be due to oxidation and reduction procedures, as evidenced from cyclic voltammetry measurements. Hence, silk fibroin protein could be used as a biomaterial for bio‐memristor devices for applications in advanced bio‐inspired very large scale integration circuit design as well as in biologically inspired synapse links for energy‐efficient neuromorphic computing.     

A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NORtype four-level cell

In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm² die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-μm CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 μs/Byte programming speed     

Floating memristor emulator with subthreshold region

Memristor which is recently discovered and known as missing circuit element is an important for memory, nonlinear and neuromorphic circuit designs. Modeling of memristor devices is essential for memristor based circuit design. In this paper, compact memristor which has high memristance value is introduced. The simulations are completed in LTspice program and expected results are obtained applying sinusoidal. Two memristor emulators are connected in serial, in parallel and promising results presented. The simulation results of applying positive pulse train to both of terminals of memristor are showed. The simulations of the proposed emulator showed the expected memristor characteristics.     

Synaptic Learning and Memory Functions Achieved Using Oxygen Ion Migration/Diffusion in an Amorphous InGaZnO Memristor

A single synaptic device with inherent learning and memory functions is demonstrated based on an amorphous InGaZnO (α‐IGZO) memristor; several essential synaptic functions are simultaneously achieved in such a single device, including nonlinear transmission characteristics, spike‐rate‐dependent and spike‐timing‐dependent plasticity, long‐term/short‐term plasticity (LSP and STP) and “learning‐experience” behavior. These characteristics bear striking resemblances to certain learning and memory functions of biological systems. Especially, a “learning‐experience” function is obtained for the first time, which is thought to be related to the metastable local structures in α‐IGZO. These functions are interrelated: frequent stimulation can cause an enhancement of LTP, both spike‐rate‐dependent and spike‐timing‐dependent plasticity is the same on this point; and, the STP‐to‐LTP transition can occur through repeated “stimulation” training. The physical mechanism of device operation, which does not strictly follow the memristor model, is attributed to oxygen ion migration/diffusion. A correlation between short‐term memory and ion diffusion is established by studying the temperature dependence of the relaxation processes of STP and ion diffusion. The realization of important synaptic functions and the establishment of a dynamic model would promote more accurate modeling of the synapse for artificial neural network.     

新型忆阻器混沌电路及其在图像加密中的应用

忆阻器是一种拥有记忆功能的电阻,目前忆阻器的研究热点及难点在于新模型的建立以及相关方面的应用。该文提出一种基于双曲正弦函数的新型磁控忆阻器模型,通过分析电压和电流的相轨迹关系,发现其具有典型的忆阻器电压-电流特性曲线。利用新建的忆阻器模型构造新型忆阻混沌系统,通过数值仿真绘出新系统的相轨迹图、分岔图、Lyapunov 指数谱等,分析了不同参数时系统的混沌演化过程。另外,基于电路仿真软件Multisim研制了实验仿真电路, 该电路结构简单、易于实际制作,且仿真实验与理论分析结论十分吻合,证实了提出的忆阻混沌系统电路在物理上是可以实现的。最后,利用新系统混沌序列对图像进行加密,重点分析了加密直方图、相邻像素相关性以及抗攻击能力与密钥敏感性,结果表明新系统对图像密钥及明文都非常敏感,密钥空间较大,新提出的忆阻混沌系统应用于图像加密具有较高的安全性能。     

Ten States of Nonvolatile Memory through Engineering Ferromagnetic Remanent Magnetization

Emerging nonvolatile multilevel memory devices have been regarded as a promising solution to meet the increasing demand of high‐density memory with low‐power consumption. In particular, decimal system of the new computers instead of binary system could be developed if ten nonvolatile states are realized. Here, a general remanent magnetism engineering method is proposed for realizing multiple reliable magnetic and resistance states, not depending on a specific material or device structure. Especially, as a proof‐of‐concept demonstration, ten states of nonvolatile memory based on the manipulation of ferromagnetic remanent magnetization have been revealed in both Co/Pt magnetic multilayers with strong perpendicular magnetic anisotropy and MgO‐based magnetic tunneling junctions at room temperature. Considering ferromagnets have been one of the key factors that enabled the information revolution from its inception, this state‐of‐the‐art remanent magnetism engineering approach has a very broad application prospect in the field of spintronics.     

Biorealistic Implementation of Synaptic Functions with Oxide Memristors through Internal Ionic Dynamics

Memristors have attracted broad interest as a promising candidate for future memory and computing applications. Particularly, it is believed that memristors can effectively implement synaptic functions and enable efficient neuromorphic systems. Most previous studies, however, focus on implementing specific synaptic learning rules by carefully engineering external programming parameters instead of focusing on emulating the internal cause that leads to the apparent learning rules. Here, it is shown that by taking advantage of the different time scales of internal oxygen vacancy (V_O) dynamics in an oxide‐based memristor, diverse synaptic functions at different time scales can be implemented naturally. Mathematically, the device can be effectively modeled as a second‐order memristor with a simple set of equations including multiple state variables. Not only is this approach more biorealistic and easier to implement, by focusing on the fundamental driving mechanisms it allows the development of complete theoretical and experimental frameworks for biologically inspired computing systems.     

Current-Sweep Operation on Nonlinear Selectorless RRAM for Multilevel Cell Applications

Bilayer selectorless resistive random-access memories (RRAM) have been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without additional transistor or a selector integration. The bilayer structures, i.e. high-k layer/low-k layer stacks, are highly scalable while suppressing the sneak path currents (SPC) and reading error in the crossbar RRAM array. The nonlinearity (NL) modulation is also investigated by different operating schemes, and a multilevel cell application is demonstrated with the current-sweep method. The results provide additional insights into the development and optimization of bilayer selectorless RRAMs with high nonlinearity, good memory window, and low switching energy (∼ 40 pJ/bit), which enable the high-density storage and low-power crossbar array memory applications.     

High-voltage management in single-supply CHE NOR-type flash memories

In a flash memory, a number of voltage levels different from V/sub DD/ are needed to perform the required operations (read, program, and erase) on the array cells. In the case of single-supply memory devices, voltages higher than V/sub DD/ as well as negative voltages, which are referred to as high voltages (HVs), must be produced on-chip. This paper aims at giving the reader an overview of how HVs are generated and managed in single-supply NOR-type flash memories programmed by channel hot-electron injection. Both schemes used for conventional (i.e., bilevel) memory devices and schemes designed to meet multilevel memory requirements are addressed.     

忆阻器的建模及高精度忆阻值读写电路的设计

使用现有电路元件设计了一种荷控忆阻器的理论模型。由于把忆阻器应用于存储器、神经网络、信号处理等领域均涉及到忆阻器的读写操作,并且目前忆阻器大多是数字量0和1的操作,没有模拟量的操作。所以利用了荷控忆阻器的电荷特性,给出一种描述如何读取忆阻器的模拟忆阻值的方法。利用了荷控忆阻器的频率特性,设计了一个反馈式忆阻值写电路,该电路能够在忆阻器的阻态范围内进行任意模拟量的写操作。仿真结果验证了设计的正确性。     

Limitations and challenges of multigigabit DRAM chip design

This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V_T) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-V_T, dynamic V_T, and node-boosting schemes