A quick intelligent page-programming architecture and a shieldedbitline sensing method for 3 V-only NAND flash memory

This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-μm NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-μs random access time with a 2.7-V power supply. The page-programming is completed after the 40-μs program and 2.8-μs verify read cycle is iterated 4 times. The block-erasing time is 10 ms     

High-voltage management in single-supply CHE NOR-type flash memories

In a flash memory, a number of voltage levels different from V/sub DD/ are needed to perform the required operations (read, program, and erase) on the array cells. In the case of single-supply memory devices, voltages higher than V/sub DD/ as well as negative voltages, which are referred to as high voltages (HVs), must be produced on-chip. This paper aims at giving the reader an overview of how HVs are generated and managed in single-supply NOR-type flash memories programmed by channel hot-electron injection. Both schemes used for conventional (i.e., bilevel) memory devices and schemes designed to meet multilevel memory requirements are addressed.     

Quick address detection of anomalous memory cells in a flash memorytest structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test     

A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme     

A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memoryfor mass storage applications

For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm² die size and a 1.1 μm² effective cell size     

A 3.3 V 32 Mb NAND flash memory with incremental step pulseprogramming scheme

While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm² die size, improved yields, and a simple process with 0.5 μm CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA     

A 256-Mb multilevel flash memory with 2-MB/s program rate for massstorage applications

A 256-Mb flash memory is fabricated with a 0.25-μm AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm² die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell V_th. The effect of adjacent memory cell's V_th is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell V_th. In the -5-75°C range, memory threshold V_th deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector     

Effects of floating-gate interference on NAND flash memory celloperation

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V _T shift of a cell proportional to the V_T change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-μm design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.     

A simple and efficient self-limiting erase scheme for highperformance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells     

A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NORtype four-level cell

In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm² die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-μm CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 μs/Byte programming speed     

Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V_pp) switching and generation for low-voltage NAND flash memories, this paper describes a V _(pp) switch, row decoder, and charge-pump circuit. The proposed nMOS V_pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V _pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V_pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V_pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 μA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%     

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

基于SiGe量子点实现增强F-N隧穿的低压闪速存储器

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which the cells are programmed. By adopting the proposed page architecture, the number of neighbor cells that are programmed after programming a selected cell in BL direction as well as their amount of T/th shift during programming can be suppressed largely without increasing memory array size. Compared to conventional architecture it leads to a reduction of BL-BL cell-to-cell interference by almost 100%, and of WL-WL and diagonal cell-to-cell interferences by 50% at the 60 nm technology node. The proposed architecture enables also to improve average MLC program speed performance by 11% compared with conventional architecture, thanks to its fast LSB program performance.     

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm/sup 2/ die size and a 0.044-/spl mu/m/sup 2/ effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V/sub CC/ in order to avoid program disturbance issues.     

A multilevel approach toward quadrupling the density of flashmemory

A multilevel scheme is presented that explores the possibility of quadrupling flash EEPROM storage density. Sixteen levels (4 bits/cell) of charge are stored in existing NOR stacked gate devices. A distinction is made between logical threshold voltages (as seen by the sense amplifier) and transistor threshold voltages (as defined by the gate characteristics), and precise programming gives distinct logical threshold voltage distributions, whereas transistor threshold voltage distributions are contained in a small 2.5 V range and kept low so that logical distributions survive a ten-year equivalent data retention bake     

A negative Vth cell architecture for highly scalable,excellently noise-immune, and highly reliable NAND flash memories

A new, negative V_th cell architecture is proposed where both the erased and the programmed state have negative V_th. This architecture realizes highly scalable, excellently noise-immune, and highly reliable NAND flash memories. The program disturbance that limits the scaling of a local oxidation of silicon (LOCOS) width in a conventional NAND-type cell is drastically reduced. As a result, the scaling limit of the LOCOS width decreases from 0.56 to 0.45 μm, which leads to 20% isolation width reduction. The proposed cell is essential for the future scaled shallow trench isolated cells because improved program disturb characteristics can be obtained irrespective of the process technology or feature size. New circuit techniques, such as a PMOS drive column latch and a V_cc-bit-line shield sensing method are also utilized to realize the proposed cell operation. By using these novel circuit technologies, array noise, such as a source-line noise and an inter bit line capacitive coupling noise, are eliminated. Consequently, the V_th fluctuation due to array noise is reduced from 0.7 to 0.1 V, and the V_th distribution width decreases from 1.2 to 0.6 V. In addition to the smaller cell size and the high noise immunity, the proposed cell improves device reliability. The read disturb time increases by more than three orders of magnitude, and a highly reliable operation can be realized