基于等价性形式验证的逻辑综合引擎设计研究

本文描述了一个基于等价性验证的逻辑综合引擎，它实现了从RTL级到网表级的综合。设计验证系统的初衷是验证给定设计从RTL级到网表级自动综合后电路的正确性，所以综合引擎本身的正确性是本文首要关注的问题。为了提高等价性验证引擎的工作效率，本文还提出并实现了一系列保持电路相似性的方法。最后，本文以SYNOPSYS的等价性验证工具FORMALITY作为比较，试验结果表明本系统是有效的。     

Achieving SCA Conformance Testing with Model-Based Testing

Time-to-market and implementation cost are high-priority considerations in the automation of digital hardware design. Nowadays, digital signal processing applications are implemented into fixed-point architectures due to its advantage of manipulating data with lower word-length. Thus, floating-point to fixed point conversion is mandatory. This conversion is translated into optimizing the integer word length and fractional word length. Optimizing the integer word-length can significantly reduce the cost when the application is tolerant to a low probability of overflow. In this paper, a new selective simulation technique to accelerate overflow effect analysis is introduced. A new integer word-length optimization algorithm that exploits this selective simulation technique is proposed to reduce both implementation cost and optimization time. The efficiency of our proposals is illustrated through experiments, where selective simulation technique allows accelerating the execution time of up to 1200 and 1000 when applied on Global Positioning System and on Fast Fourier Transform part (FFT) of Orthogonal Frequency Division Multiplexing chain respectively. Moreover, applying the optimization algorithm on the FFT part leads to a cost reduction between 17 to 22 % with respect to interval arithmetic and an acceleration factor of up to 617 with respect to classical max-1 algorithm.     

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits

A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a novel methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to be compatible with the corresponding precomputed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences.     

Resonators in Open-Loop Sigma–Delta Modulators

In this paper, we introduce the modulo resonator for use in analog-to-digital open-loop sigma-delta modulators (OLSDMs). The OLSDM presented in this paper is intended for use in high-accuracy (14-bit) high-speed analog-to-digital converters. The modulo resonator is used with a modulo notch filter to insert a zero in the noise transfer function at a nonzero frequency. The effect of finite gain in modulo integrators and resonators is described and verified through simulation. The modulo resonator and a previously published modulo integrator are used in a behavioral model of a switched-capacitor fifth-order OLSDM with more than 13-bit effective number of bits for an oversampling ratio of four. We prove for the N -order OLSDM that the number of bits in the quantizer (B) must be larger than N to ensure equivalence between open-loop sigma-delta modulation and sigma-delta modulation.     

基于二元域等效的RS码编码参数盲识别

现代数字通信中常常进行信道编码识别处理.目前RS（Reed-Solomon,RS）码盲识别需对高阶域下所有谱分量进行求取,计算较为复杂,因此提出了一种基于二元域等效的识别方法.首先根据有限域性质将RS码等效为二元域上的线性分组码,然后建立码长、信息分组长度、生成多项式和本原多项式的关联模型.通过遍历各阶本原多项式,并验证二元线性分组码的校验向量,完成各参数的联合识别.仿真结果和理论分析表明,该方法在提升抗误码性能的同时有效减少了计算量,可用于智能通信和通信侦察等系统中.     

Quantized FIR filter design using compensating zeros

This article presents a design method for translating a finite impulse response (FIR) floating-point multiplierless filter design. Conventional wisdom dictates that finite word-length (i.e., quantization) effects can be minimized by dividing a filter into smaller, cascaded sections. In this design method, it is shown how to quantize the cascaded sections so that the finite word-length effects in one section are guaranteed to compensate for the finite word-length effects in the other section. This simple method called, "compensating zeros," ensures that: (1) the quantized filter's frequency response closely matches the unquantized filter's frequency response (in both magnitude and phase); and (2) the required hardware remains small and fast.     

一种自动生成状态机RTL代码的方法

集成电路设计中,状态机的代码实现具有一定规律性.根据该规律通过某种方法自动生成状态机RTL代码,可以提高设计设计效率.此项方法首先由Matlab中的Stateflow工具输入状态转移图,利用基于Tcl/Tk的软件提取其中有用信息,再进行状态机RTL代码生成,完成转换过程.该软件的成功设计和应用证明了此方法的可行性和实用性.     

A C-testable carry-free divider

In this paper, the design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers which used carry-propagate adders/subtractors. These dividers are slow because of their O(W²) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two's-complement form is shown to be not C-testable. It is modified to be linear-testable (in word-length) instead of exponential time required for exhaustive testing of all possible combinations at its inputs. We conclude that the number of test vectors needed is 99 for C-testing of the divider array and (3W+10) for linear testing of the converter. The hardware overhead required to make the divider C-testable and the on-the-fly converter linear testable is also shown to be nominal     

Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes

In this paper, we propose an improvement of the normalized min-sum (MS) decoding algorithm and novel MS decoder architectures with reduced word length using nonuniform quantization schemes for low-density parity-check (LDPC) codes. The proposed normalized MS algorithm introduces a more exact adjustment with two optimized correction factors for check-node-updating computations, while the conventional normalized MS algorithm applies only one correction factor. The proposed algorithm provides a significant performance gain without any additional computation or hardware complexity. The finite word-length analysis in implementing an LDPC decoder is a very important factor since it directly impacts the size of memory to store the intrinsic and extrinsic messages and the overall hardware area in the partially parallel LDPC decoder. The proposed nonuniform quantization scheme can reduce the finite word length while achieving similar performances compared to a conventional quantization scheme. From simulation results, it is shown that the proposed 4-bit nonuniform quantization scheme achieves an acceptable decoding performance, unlike the conventional 4-bit uniform quantization scheme. Finally, the proposed MS decoder architectures by the nonuniform quantization scheme provide significant reductions of 20% and up to 8% for the memory area and combinational logic area, respectively, compared to the conventional 5-bit ones.      

Fault Current Limiter Based on Resonant Circuit Controlled by Power Semiconductor Devices

This work presents a resonant fault current limiter (FCL) controlled by power semiconductor devices. Initially the operation of two ideal resonant circuit topologies as fault current limiter are discussed. The analysis of these circuits is used to derive an alternative topology to the fault current limiter based on the connection of a series and a parallel resonant circuit. Digital models are implemented in the SimPowerSystem/Matlab simulation package to investigate the performance of the proposed FCL to protect transmission and distribution electric networks against short circuit currents. Transfer functions of the linear limiter models are used to identify the effect of each element of the FCL over its stability and its transient response. The developed analysis will be used to derive modifications in the FCL topology in such a way to improve their dynamic response.     

K-terminal reliability in ring networks

The authors present a new formula for computing K-terminal reliability in a communication network whose stations and links (vertices and edges) form a network graph G having a ring topology, where K-terminal reliability is the probability R_K(G) that a subset of R specific terminal stations in G can communicate. This new formula is applied to three Fiber Distributed Data Interface (FDDI) ring-network topologies, and for each topology the authors derive closed-form polynomial expressions of R_K(G) in terms of the failure probabilities of links, network ports, and station common units. The authors define the concept of the K-minimal Eulerian circuit and use combinations of these circuits to obtain K-graphs and their resulting dominations, thus extending the use of K-graphs to ring networks in which data messages, tokens, or other control frames traverse operative network links with an Eulerian tour. Distinct K-graphs having a nonzero sum of dominations are called noncanceled K-graphs and correspond exactly to terms in closed-form polynomial expressions of R_K(G). The authors show that trees have only one K-graph and that counter-rotating dual rings and rings of trees have at most 2K+1 noncanceled R-graphs. These results contribute the first closed-form polynomial R-terminal reliability expressions for the ring-of-trees topology. The results are useful in evaluating dependability, reliability, availability, or survivability of token rings and similar networks     

On the factorization of polynomials and direct sum properties in integer polyomial rings

In our recent work, we solved the word sequence length constraint problem associated with number theoretic transforms defined in finite integer rings. This is based on the American-Indian-Chinese extension of the Chinese remainder theorem. This work builds further on the results by extending them to the domain of integer polynomial rings. The theory of polynomial factorization and the resulting direct sum property are studied in depth. The emphasis is on the theory of computational algorithms for processing sequences defined in finite integer and complex integer rings.     

数据字长对GPS信号捕获跟踪性能影响分析

数据字长对GPS接收机性能和硬件资源消耗有着重要影响,以循环相关捕获算法为例,利用线性方法建立GPS接收机各部分量化误差模型,讨论算法实现中各模块数据字长对信噪比的影响,给出了误差表达式,确定了系统性能与资源消耗的最优结合点.软件接收机仿真测试结果表明,该方法分析结果正确有效,能够为捕获跟踪电路的FPGA实现提供工程设计参考.     

Estimates of the distance distribution of codes and designs

We consider the problem of bounding the distance distribution for unrestricted block codes with known distance and/or dual distance. Applying the polynomial method, we provide a general framework for previously known results. We derive several upper and lower bounds both for finite length and for sequences of codes of growing length. Asymptotic results in the paper improve previously known estimates. In particular, we prove the best known bounds on the binomiality range of the distance spectrum of codes with a known dual distance