Leakage Biased pMOS Sleep Switch Dynamic Circuits

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology     

A very high-speed CMOS 4-2 compressor using fully differential current-mode circuit techniques

This paper presents a new high-speed CMOS 4-2 compressor which is an essential part in fast digital arithmetic integrated circuits. Current-mode techniques have been used to improve the overall performance of the compressor. New fully differential proposed circuit improves speed up to 45% also reduces occupied area in comparison to other high-speed conventional compressor circuits. To evaluate the performance of the proposed circuit, two other structures have been chosen and all of the circuits have been simulated in 0.18 μm standard TSMC CMOS process with 1.8 V power supply voltage.     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Employing multiple supply voltages (multi- V_DD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-V_th) level converters are proposed in this paper. The new multi-V_th level converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a 0.18- mum TSMC CMOS technology.     

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.     

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.     

Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits

Power gating has been widely used to reduce subthreshold leakage. However, the efficiency of power gating degrades very fast with technology scaling, which we demonstrate by experiment. This is due to the gate leakage of circuits specific to power gating, such as storage elements and output interface circuits with a data-retention capability. A new scheme called supply switching with ground collapse is proposed to control both gate and subthreshold leakage in nanometer-scale CMOS circuits. Compared to power gating, the leakage is cut by a factor of 6.3 with 65-nm and 8.6 with 45-nm technology. Various issues in implementing the proposed scheme using standard-cell elements are addressed, from register transfer level to layout. These include the choice of standby supply voltage with circuits that support it, a power network architecture for designs based on standard-cell elements, a current switch design methodology, several circuit elements specific to the proposed scheme, and the design flow that encompasses all the components. The proposed design flow is demonstrated on a commercial design with 90-nm technology, and the leakage saving by a factor of 32 is observed with 3% and 6% of increase in area and wirelength, respectively.     

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “transregional” MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling     

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.     

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valuedMOS current-mode circuits with dual-rail source-coupled logic

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54×51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-μm standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit     

An ultra-low-voltage ultra-low-power CMOS active mixer

The scaling of CMOS technology has greatly influenced the design of analog and radio-frequency circuits. In particular, as technology advances, due to the use of lower supply voltage the available voltage headroom is decreased. In this paper, after a brief overview of conventional low-power CMOS active mixer structures, we introduce an active mixer structure with sub-mW-level power consumption that is capable of operating from a supply voltage comparable or lower than the threshold voltage of the transistor. In addition, the proposed architecture provides a performance and conversion gain (CG) that compares favorably or exceeds those of the state-of-the-art designs. As a proof-of-concept, a wide-band DC to 8.5 GHz down-conversion mixer is designed and fabricated in a 90-nm CMOS process. Measurement results show that the mixer achieves a CG as high as 18 dB while consuming 98 μW from a 0.3-V supply.     

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies.     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology

In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to provide higher operating speed with lower power supply voltage. However, regarding compatibility with the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes face the gate-oxide reliability problems in the interface circuits due to the voltage levels higher than normal supply voltage (1$,times,$ VDD) required by earlier applications. As a result, mixed-voltage I/O circuits realized with only thin-oxide devices had been designed with advantages of less fabrication cost and higher operating speed to communicate with the circuits at different voltage levels. In this paper, two new mixed-voltage-tolerant crystal oscillator circuits realized with low-voltage CMOS devices are proposed without suffering the gate-oxide reliability issues. The proposed mixed-voltage crystal oscillator circuits, which are one of the key I/O cells in a cell library, have been designed and verified in a 90-nm 1-V CMOS process, to serve 1-V/2-V tolerant mixed-voltage interface applications.      

高低压兼容单片CMOS驱动器的设计

采用标准n阱硅栅等平面CMOS工艺,将耐压大于200V、吸收电流大于200mA的高压功率VMOS器件与工作在5V电源电压的CMOS控制电路兼容在同一个硅芯片上。分析了电路设计及工艺措施,证明这种技术可以低成本地制作各种低高压兼容电路。     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the process and temperature variations. For the sake of not only enlarging the write margin but also reducing power consumption and speed overhead, the divided dynamic power-line scheme based on a charge sharing is adopted. Test chips of 512-Kb SRAM macros and isolated memory cell TEGs are fabricated using 45-nm bulk CMOS technology. Two types of 6-T SRAM cells, whose sizes were 0.245 mum² and 0.327 mum² were designed and evaluated. From the measurement results, we achieved over 100-mV improvement for static noise margin, and 35 mV for write margin for both SRAM cells at 1.0-V worst condition by using assist circuitry. It enables the wordline level to keep higher voltage at the slowest condition than the typical process condition, which results in 83% improvement of the cell current compared with the conventional assist circuit. Furthermore, the minimum operating voltage in the worst case condition was improved by 170 mV, confirming a high immunity against process and temperature variations with less than 10% area overhead.     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

An audio amplifier providing up to 1 Watt in standard digital 90-nm CMOS

An audio amplifier in a standard 90-nm dual gate-oxide CMOS technology is designed for direct connection to the battery in a mobile phone. Special techniques have been applied to run it from a supply voltage of up to 5.5 V. The circuit does not require a dedicated supply voltage generator; it can be integrated on the same chip with the digital signal processor, and provides high output power, good power supply rejection, and good efficiency.