Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems

Wepresent the Serra Run-Time Scheduler Synthesis and AnalysisTool which automatically generates a run-time scheduler froma heterogeneous system-level specification in both Verilog HDLand C. Part of the run-time scheduler is implemented in hardware,which allows the scheduler to be predictable in being able tomeet hard real-time constraints, while part is implemented insoftware, thus supporting features typical of software schedulers. Serra's real-time analysis generates a priority assignment forthe software tasks in the mixed hardware-software system. Thetasks in hardware and software have precedence constraints, resourceconstraints, relative timing constraints, and a rate constraint.A heuristic scheduling algorithm assigns the static prioritiessuch that a hard real-time rate constraint can be predictablymet. Serra supports the specification of critical regions insoftware, thus providing the same functionality as semaphores.We describe the task control/data-flow extraction,synthesis of the control portion of the run-time scheduler inhardware, real-time analysis and priority scheduler template.We also show how our approach fits into an overall tool flowand target architecture. Finally, we conclude with a sample applicationof the novel run-time scheduler synthesis and analysis tool toa robotics design example.     

Reliable real-time task scheduler based on Rocket Queue architecture

This paper presents the design of an improved task scheduler for real-time and safety-critical systems, where it is important to deal with real-time requirements and reliability requirements simultaneously. The proposed scheduler implements EDF algorithm for the optimal scheduling of hard real-time tasks, which is essential for real-time operating systems. The proposed task scheduler allows removing any task from the queue according to task ID and regardless of the actual position of the task within the queue, which is important for flexibility of the scheduler for its future extensions. Both operations of the scheduler, i.e. task adding and task killing take always constant time (two clock cycles) to execute regardless of the actual or the maximum number of tasks within the scheduler. The scheduler was verified using simplified version of UVM and applying millions of instructions with randomly generated sort values. The scheduler, implemented in a form of a coprocessor, was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency. There are two improvements proposed that can significantly reduce resource costs of the scheduler, which is achieved by replacing static deadlines with dynamic deadlines and using a new Rocket Queue architecture for sorting of the tasks according to their deadline values. When both improvements are applied simultaneously, the total ALM cost savings are in the range from 42,59% to 60,18% and the total amount of registers is reduced by 73,74% to 74,87%, depending on the scheduler capacity. The spared resources are then used for implementation of two different variations of TMR in order to increase fault tolerance of the scheduler. The resource cost reductions achieved also indirectly increase the reliability of such scheduler because of reduced probability that a fault occurs.     

A heterogeneous built-in self-repair approach using system-level synthesis flexibility

Summary and Conclusions -A novel methodology is proposed for designing fault-tolerant real-time multi-processor systems-on-a-chip to achieve optimal productivity. The methodology employs the heterogeneous built-in-self-repair (BISR) based on graceful degradation and yield enhancement techniques as an embedded optimization engine. The technique exploits the flexibility provided in task-level scheduling and algorithm selection steps. A hardware fault model is developed for modern super-scalar processors and multi-processors which enables an efficient treatment of the synthesis and compilation goals. For the first time, heterogeneous BISR is used at the task level. The key idea is to adapt scheduling and algorithm selection to the available nonfaulty resources. If there is a fault in memory, the algorithms that use less memory are selected and the scheduler exploits the other abundant resource, viz, the processors, more vigorously to compensate for the loss of part of memory. Similarly, a fault in a processor is backed up by memory. The synthesis approach minimizes the degradation in performance for single or multiple faults using simulated annealing-based algorithm selection, scheduling, and assignment algorithms. On the large set of examples this adaptive algorithm selection and scheduling technique has achieved important improvement of throughput compared to conventional nonadaptive schemes. The experimental results also indicate that important improvement in productivity can be achieved by using the extra throughput gained from the technique.     

Earliest Deadline First Scheduling with Active Buffer Management for Real-Time Traffic in the Internet

We studied the problem of QoS guarantee for differentiated services. A two-level hierarchical scheduling framework was deployed to separate QoS metrics. Due to its desirable property of minimizing the maximum packet lateness, the Earliest Deadline First (EDF) scheduling was adopted to provide the in-class scheduling for the time-sensitive traffic. We employed an EDF scheduler combined with an active buffer management scheme (CHOKe) to improve the fairness of resource allocation and to maintain a good delay performance for real-time applications. Simulation results showed that the proposed scheme can achieve a better delay performance and make a more fair bandwidth allocation between the real-time TCP and UDP connections than the First Come First Served (FCFS) scheduling with the drop-tail buffer management which is commonly deployed in traditional IP routers.     

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems

Dynamic voltage scaling has been widely acknowledged as a powerful technique for trading off power consumption and delay for processors. Recently, variable-frequency (and variable-voltage) parallel and serial links have also been proposed, which can save link power consumption by exploiting variations in the bandwidth requirement. This provides a new dimension for power optimization in a distributed embedded system connected by a voltage-scalable interconnection network. At the same time, it imposes new challenges for variable-voltage scheduling as well as flow control. First, the variable-voltage scheduling algorithm should be able to trade off the power consumption and delay jointly for both processors and links. Second, for the variable-frequency network, the scheduling algorithm should not only consider the real-time constraints, but should also be consistent with the underlying flow control techniques. In this paper, we address joint dynamic voltage scaling for variable-voltage processors and communication links in such systems. We propose a scheduling algorithm for real-time applications that captures both data flow and control flow information. It performs efficient routing of communication events through multihops, as well as efficient slack allocation among heterogeneous processors and communication links to maximize energy savings, while meeting all real-time constraints. Our experimental study shows that on an average, joint voltage scaling on processors and links can achieve 32% less power compared with voltage scaling on processors alone     

基于多核处理器的节能任务调度方法

由于关系到系统的安全性及散热代价等方面,能耗问题已经成为嵌入式系统研究的重点。对于多核处理器上具有依赖关系的周期性硬实时任务,设计了一种基于动态电压调节的节能任务调度方法。该方法首先用RDAG算法将任务独立化,然后以功耗最低为原则,采用遗传算法确定任务映射。基于Intel PXA270功耗模型,采用了几个随机任务集进行仿真实验,结果表明该方法比现有的方法节省了20%～30%的能耗。     

用于资源动态预留的航天测控资源配置优化算法

针对航天测控资源配置优化问题这类约束条件繁杂且数量众多的组合优化问题,提出了可用于资源动态预留的航天测控资源配置优化算法。具体来讲,考虑测控设备和航天器执行任务的唯一性约束以及时间窗口冲突约束,建立了基于原子型任务调度的0-1整数规划模型;设计了能将实际需求和求解算法进行解耦的求解框架,并基于最大化利用测控资源的思想获得了可回溯的并行最佳优先搜索算法。仿真结果表明,所提算法达到了能在国内东部、西部、南部和北部四大测控区域中更加均衡地动态预留出更多、更重要测控设备的资源配置优化效果。     

System-Level Synthesis Using Evolutionary Algorithms

In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the selection of the architecture (allocation) including general purpose and dedicated processors, ASICs, busses and memories, (2) the mapping of the specification onto the selected architecture in space (binding) and time (scheduling), and (3) the design space exploration with the goal to find a set of implementations that satisfy a number of constraints on cost and performance. Existing methodologies often consider a fixed architecture, perform the binding only, do not reflect the tight interdependency between binding and scheduling, do not consider communication (tasks and resources), or require long run-times preventing design space exploration, or yield only one implementation with optimal cost. Here, a model is introduced that handles all mentioned requirements and allows the task of system-synthesis to be specified as an optimization problem. The application and adaptation of an Evolutionary Algorithm to solve the tasks of optimization and design space exploration is described.     

A multiprocessor-oriented power-conscious scheduling algorithm for periodic tasks

With the rapid development of advanced technology in VLSI circuit designs, many processors could provide dynamic voltage scaling (DVS) to save power consumption when the supply voltage is allowed to be lower. In this paper, we propose a multiprocessor-oriented power-conscious scheduling algorithm for the real-time periodic tasks with task migration constrained scheme. We classify periodic tasks into fixed tasks and migration tasks, and limit the number of migration tasks and the number of destination processors which execute migration tasks. The proposed algorithm is made up of two steps. Firstly, choosing a processor to sort all of the periodic tasks in a non-increasing order according to task utilization, afterwards, allocating them to other processors. Secondly, scheduling the migration tasks with a virtual execution windows policy, and then scheduling the fixed tasks with EDF algorithm. The experiment results show that compared with arbitrary task migration policy and no task migration allowed policy, the power consumption in multiprocessor real-time periodic tasks scheduling is lowered significantly with the proposed algorithm.     

Flowmeter for QoS provision in packet switched networks

A flowmeter is a set of traffic-related variables associated with a connection established in a network node as a result of the connection setup. Comprehensive quality-of-service provision to each packet flow is the purpose of flowmeter-based dynamic packet scheduling. The earliest deadline first (EDF) scheduling algorithm is adopted for rate allocation, delay control, and flow control. A gas pressure admission control algorithm is also presented to simplify EDF admission test. The delay performance of the scheduler is evaluated on a subnetwork of the Internet     

Downlink scheduling in a cellular network for quality-of-service assurance

We consider the problem of scheduling data in the downlink of a cellular network over parallel time-varying channels, while providing quality-of-service (QoS) guarantees to multiple users in the network. We design simple and efficient admission control, resource allocation, and scheduling algorithms for guaranteeing requested QoS. In our design, a joint Knopp and Humblet (K&H)/round robin (RR) scheduler, composed of K&H scheduling and RR scheduling, utilizes both multiuser and frequency diversity to achieve capacity gain when delay constraints are loose or moderate. However, for tight delay constraints, an additional reference channel scheduler is required to obtain additional frequency diversity gain. The key advantage of our formulation is that the desired QoS constraints can be explicitly enforced by utilizing the concept of effective capacity.     

异构多处理器系统的混合任务调度算法

针对实时异构系统的任务调度问题,提出了一种异构多处理器系统的混合实时任务调度算法.该算法采用带有非周期服务器的EDF( Earliest Deadline First)算法来调度单处理器上的任务集,可充分利用处理器的计算带宽.采用启发式搜索算法来进行任务的分配,以最大剩余计算带宽为搜索指标,可确保各处理器的负载尽量平衡...     

An exploration of aggregation convergecast scheduling

We consider the problem of aggregation convergecast scheduling as it applies to wireless networks. The solution to aggregation convergecast satisfies the aggregation process, expressed as precedence constraints, combined with the impact of the shared wireless medium, expressed as resource constraints. Both sets of constraints influence the routing and scheduling. We propose an aggregation tree construction suitable for aggregation convergecast that is a synthesis of a tree tailored to precedence constraints and another tree tailored to resource constraints. Additionally, we show that the scheduling component can be modeled as a mixed graph coloring problem. Specifically, the extended conflict graph is introduced, and through it, a mapping from aggregation convergecast to mixed graphs is described. In the mixed graph, arcs represent the precedence constraints and edges represent the resource constraints. The mixed graph chromatic number corresponds to the optimal schedule length. Bounds for the graph coloring are provided and a branch-and-bound strategy is subsequently developed from which we derive numerical results that allow a comparison against the current state-of-the-art heuristic.     

A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis

In this paper we propose a generalized technique to count the required number of registers in a schedule which supports overlapped scheduling and can be applied to the case where a general digit-serial data format is used. This technique is integrated into an integer linear programming (ILP) model for time-constrained scheduling. In the ILP model, appropriate processors of certain data formats are chosen from a library of processors and data format converters are automatically inserted between processors of different data formats if necessary. Then the required number of registers for each data format is evaluated correctly by the proposed technique. Hence an optimal architecture for a given digital signal processing algorithm is synthesized where the cost of registers as well as the cost of processors and data format converters are minimized. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8% savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.     

行为综合功能流水线中的负载平衡蚁群调度算法

在专用集成电路高层次综合中,功能流水线是提高算法描述执行速度的关键技术.针对时间约束和资源约束的两类行为综合功能流水线调度问题,提出了一种基于蚁群优化(ACO)的调度算法.LB-ACO算法将ACO算法与力向算法相结合,使用修改的力向公式定义局部试探因子,用个体调度结果的质量来更新全局试探因子.实验结果表明,LB-ACO算法在保证较低的时间复杂度O(cn2)的前提下,获得接近最优的调度结果.     

A time Petri net-based method for embedded hard real-time software synthesis

Over the last few years, embedded software synthesis has drawn much attention. However, few works deal with software synthesis for hard real-time systems considering arbitrary inter-tasks precedence and exclusion relations. Code generation for meeting all timing and resource constraints is not a trivial task. Thus, this research area has several open issues, mainly related to generation of predictable-guaranteed scheduled code. The method proposed in this paper starts from a high-level specification, and automatically translates such specification into a time Petri net model; this model is adopted for finding a feasible static schedule meeting all constraints. If found, the approach generates a scheduled code, based on the found feasible schedule. Therefore, the user just enter the specification and receives, as result, the scheduled code. Thus, all intermediary phases are hidden from the users.     

可重构分组密码指令集处理器自动映射方法研究

计算资源与寄存器资源分配是可重构处理器自动并行映射的重要问题,该文针对可重构分组密码指令集处理器的资源分配问题,建立算子调度参数模型和处理器资源参数模型,研究了分组密码并行调度与资源消耗之间的约束关系;在此基础上提出基于贪婪思维、列表调度和线性扫描的自动映射算法,实现了分组密码在可重构分组密码指令集处理器上的自动映射。通过可用资源变化实验验证算法并行映射的有效性,并对AES-128算法的映射效果做了横向对比验证算法的先进性,所提自动映射算法对分组密码在可重构处理中的并行计算研究有一定的指导意义。     

An On-Line Scheduler over Hard Real-Time Communication System

By thorough research on the prominent periodic and aperiodic scheduling algorithms,anon-line hard real-time scheduler is presented,which is applicable to the scheduling of packets over a link.This scheduler,based on both Rate Monotonic,pinwheel scheduling algorithm Sr and Polling Serverscheduling algorithms,can rapidly judge the schedulability and then automatically generate a bus tablefor the scheduling algorithm to schedule the packets as the periodic packets.The implementation of thescheduler is simple and easy to use,and it is effective for the utilization of bus link.The orderly executionof the bus table can not only guarantee the performance of the hard real time but also avoid the blockageand interruption of the message transmission.So the scheduler perfectly meets the demand of hard real-time communication system on the field bus domain.     

Redundant task-allocation in multicomputer systems

A simple yet effective method for improving multicomputer multiprocessor system reliability via redundant allocation of tasks to computers (processors) is described. Given any known (nonredundant) scheduling strategy, tasks are allocated to processors statically and redundantly using a k-circular shifting (KCS) algorithm. so that if some processors fail during the execution. all tasks can be completed on the remaining processors (but at a longer time). Redundant allocation of independent tasks to identical processors (computers), subject to real-time constraints on total execution time, is discussed in detail, and analytic reliability estimates are derived. The longest processing time scheduling is given as an example of nonredundant deterministic scheduling of independent tasks. Processor utilization for redundant task-allocation is discussed and compared with standby redundancy: the authors' KCS algorithm achieves much higher processor utilization than standby redundancy     

Resource-constrained loop list scheduler for DSP algorithms

We present a new algorithm for resource-constrained scheduling for digital signal processing (DSP) applications when the number of processors is fixed and the objective is to obtain a schedule with the minimum iteration period. This type of scheduling is best suited for moderate speed applications where conservation of area and power is more important than speed. We define and make use of newgraph dependent constraints to obtain a lower bound estimate on the iteration period for any data-flow graph. By satisfying these constraints before performing the scheduling task, we can restrict the design space and can generate valid schedules in less time than previously reported. The graph dependent constraints provide a more accurate lower bound estimate on the iteration period than previously published results. This new scheduling algorithm exploits the iterative nature of DSP algorithms and uses aniterative-loop based scheduling approach. This resource scheduling algorithm has been incorporated in the Minnesota ARchitecture Synthesis (MARS) system. Our approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining to generate optimal and near optimal schedules.This research was supported by the Advanced Research Projects Agency under grant number F33615-93-C-1309 and the office of Naval Research under contract number N00014-91-J-1008.