Surface-related drain current dispersion effects in AlGaN-GaN HEMTs

Drain current dispersion effects are investigated in AlGaN-GaN HEMTs by means of pulsed, transient, and small-signal measurements. Gate- and drain-lag effects characterized by time constants in the order of 10/sup -5/-10/sup -4/ s cause dispersion between dc and pulsed output characteristics when the gate or the drain voltage are pulsed. An activation energy of 0.3 eV is extracted from temperature-dependent gate-lag measurements. We show that two-dimensional numerical device simulations accounting only for polarization charges and donor-like traps at the ungated AlGaN surface can quantitatively reproduce all dispersion effects observed experimentally in the different pulsing modes, provided that the measured activation energy is adopted as the energetic distance of surface traps from the valence-band edge. Within this hypothesis, simulations show that surface traps behave as hole traps during transients, interacting with holes attracted at the AlGaN surface by the negative polarization charge.     

Trapping Effects in the Transient Response of AlGaN/GaN HEMT Devices

In this paper, the transient analysis of an AlGaN/GaN high-electron mobility transistor (HEMT) device is presented. Drain-current dispersion effects are investigated when gate or drain voltages are pulsed. Gate-lag and drain-lag turn-on measurements are analyzed, revealing clear mechanisms of current collapse and related dispersion effects. Numerical 2-D transient simulations considering surface traps effects in a physical HEMT model have also been carried out. A comparison between experimental and theoretical results is shown. The presence of donor-type traps acting as hole traps, due to their low energy level of 0.25 eV relative to the valence band, with densities >1e20 cm^-3 (>5e12 cm^-2), uniformly distributed at the HEMT surface, and interacting with the free holes that accumulated at the top surface due to piezoelectric fields, accounts for the experimentally observed effects. Time constants next to 10 ms are deduced. Some additional features in the measured transient currents, with faster time constants, could not be associated with surface states     

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO₂ barrier.     

Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

In this paper, analytical models of drain current and small signal parameters for undoped symmetric Gate Stack Double Gate (GSDG) MOSFETs including the interfacial hot-carrier degradation effects are presented. The models are used to study the device behavior with the interfacial traps densities. The proposed model has been implemented in the SPICE circuit simulator and the capabilities of the model have been explored by circuit simulation example. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GSDG MOSFET design and the accurate proposed model can alleviate the critical problem and further improve the immunity of hot-carrier effects of DG MOSFET-based circuits after hot-carrier damage.     

Light sensitivity of current DLTS and its implications on the physics of DC-to-RF-dispersion in AlGaAs-GaAs HFETs

The light sensitivity of current deep-level transient spectroscopy (I-DLTS) is analyzed with the aim of gaining insight about the physics of surface-trap related dc-to-RF dispersion effects in AlGaAs-GaAs heterostructure field-effect transistors. I-DLTS experiments under dark reveals three surface-trap levels with activation energies 0.44 eV (h1), 0.59 eV (h2), and 0.85 eV (h3), as well as a bulk trap with activation energy 0.45 eV (e1). While the I-DLTS signal peaks associated with the two shallower surface traps h1 and h2 are suppressed by optical illumination with energy larger than the AlGaAs bandgap, that which is associated with the deepest surface trap h3 is nearly unaffected by light up to the highest intensity adopted. Two-dimensional device simulations assuming that surface traps behave as hole traps provide an interpretation for the observed different light sensitivity of surface traps, explaining it as the result of the temperature dependence of surface hole concentration and negative trap-charge density, making trap-charge modulation at increasing temperature less and less sensitive to excess carriers generated by light.     

The roles of traps in the energy loss for aged organic solar cells: A transient photovoltage study

By investigating the turn-on and turn-off photovoltage dynamics as a function of aging time, we reported the roles of traps on the energy loss in organic solar cells composing of copper phthalocyanine (CuPc)/fullerene (C60). Illuminating the device with square pulses of light, a peak of transient photovoltage after turn-on was observed after device degradation. After turn-off, the transient photovoltage first goes to the negative before settling back to zero, which is the result of electron trapping in the C60 layer before being neutralized by re-injected holes. Furthermore, by adding a tris (8-hydroxyquinolinato) aluminum buffer to prevent the traps from propagating into C60 layer, the peak after turn-on is greatly suppressed and the negative peak after turn-off vanishes, supporting the trapped electrons in the C60 layer play the critical role in the appearance of peak of the transient photovoltage.     

Modeling the effects of surface states on DLTS spectra of GaAsMESFETs

A resistance deep-level transient spectroscopy (DLTS) model which explains the effects of surface states on DLTS spectra of GaAs MESFETs is presented. The model includes both deep traps in the active channel under the gated region and the surface states on the ungated surface between the contacts of gate and source as well as gate and drain. Surface states are shown to result in minority holelike DLTS signals. The model reveals that the surface-state energy levels can be reliably determined from these holelike DLTS signals, although the concentrations cannot be accurately profiled due to the strong dependence of the peak magnitude of the holelike signals on the ungated surface conditions, in particular, the surface leakage current. The peak magnitude of the holelike signals are shown to depend strongly on the filling pulsewidth t_p used in a DLTS measurement. It is also shown that the peak magnitude decreases rapidly as the ratio of the gate length to the gate-source spacing is increased. It is expected that the model can be a useful tool for investigating the passivation effects of the ungated surface on a short-gate GaAs MESFET     

Numerical analysis of slow current transients and power compression in GaAs FETs

Two-dimensional transient simulation of GaAs MESFETs is performed when the gate voltage and the drain voltage are both changed abruptly. Quasi-pulsed current-voltage (I-V) curves are derived from the transient characteristics. It is discussed how the slow current transients (lag phenomena) and the pulsed I-V curves are affected by the existence of substrate traps and surface states. It is shown that the so-called power compression could occur both due to substrate traps and due to surface states. Effects of impact ionization of carriers on these phenomena are also discussed. It is shown that the lag phenomena and the power compression are weakened when impact ionization of carriers becomes important, because generated holes may help the traps to change their ionized densities quickly.     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

Analysis of surface state effect on gate lag phenomena in GaAsMESFET's

A two-dimensional transient simulation of the gate lag phenomenon in GaAs MESFET's has been performed. Our results show that the charge exchanges in the population of the surface states at the ungated access region of FET's are responsible for this slow transient phenomenon. The measured “hole-trap-like” DLTS signal is directly related to the re-emission of the holes, trapped during the filling pulse. Higher gate pulse can cause more serious lag phenomenon due to larger modulation of surface charge density. Devices with shorter N⁺-gate spacing and lower surface state densities are shown to have less gate lag effect     

Improvement of the drain breakdown voltage of GaAs power MESFET's by a simple recess structure

Dependence of the drain-to-source breakdown voltage on the drain structure of GaAs power FET's was investigated. It was found that the drain breakdown voltage is improved by a simple recess structure without surface n⁺contact layer. This is due to relaxation of the field at the drain region by increase of the thickness of the active epitaxial layer. The GaAs MESFET with this simple recess structure could be operated up to 24 V. There was no explicit difference in the microwave properties of both recess structure devices with and without the n⁺contact layer. As a practical device, an output power of more than 3 W with 4-dB gain is obtained at 6.5 GHz from this simple recess and cross-over structure GaAs FET.     

Low-frequency noise properties of selectively dry etched InP HEMT's

The low-frequency noise of lattice-matched InAlAs/InGaAs/InP high electron mobility transistors (HEMT's) gate recess etched with a highly selective dry etching process and with conventional wet etching were studied at different gate and drain biases for the temperature range of 77-340 K. The measurements showed a significantly lower normalized drain current 1/f noise for the dry etched HEMT's under all bias conditions. No difference in the normalized gate current 1/f noise could be observed for the two device types. By varying the temperature, four electron traps could be identified in the drain current noise spectra for both dry and wet etched devices. No additional traps were introduced by the dry etching step. The concentration of the main trap in the Schottky layer is one order of magnitude lower for the dry etched HEMT's. No hydrogen passivation of the shallow donors was observed in these devices. We presume hydrogen passivation of the deep levels as the cause for the trap density reduction. The kink effect in the dry etched HEMT's was observed to be reduced significantly compared with wet etched devices which gives further evidence of trap passivation during dry etching. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of devices for noise sensitive applications     

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600 °K by using the SILVACO¹ TCAD tools. In particular, we have studied their current-voltage characteristics (I_D-V_GS and I_D-V_DS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.     

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

We proposed here a reliability model that successfully introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.      

Self-heating and gate leakage current in a guarded MOSFET

Gate leakage current measurements of a guarded MOSFET show that device self-heating has a marked effect on the Schottky emission current. This effect can make the bias conditions for zero gate leakage current very sensitive to changes in drain voltage.     

High-electric-field effects and degradation of AlGaAs/GaAs power HFETs: a numerical study

This work presents a numerical study of high-field degradation and reliability issues of AlGaAs/GaAs power HFETs. A commercial two-dimensional drift–diffusion tool is used to investigate electric-field distributions, the effects of electron capture at the device surface under hot-carrier conditions, and the impact of drain recess scaling on such effects. Wherever experimental data are available for direct comparison, a good match is observed with our simulations. The main results of this study are (1) a validation of the hypothesis that attributes the main high-field degradation effects to electron capture over the gate–drain access region, and (2) design indications pointing out to the possibility of a reverse correlation between the gate–drain breakdown voltage and the device hot-carrier reliability.     

Two-dimensional numerical simulation of side-gating effect in GaAsMESFETs

Two-dimensional device simulations that confirm that the side-gating effect in GaAs MESFETs occurs on semi-insulating substrates containing hole traps are discussed. A negative voltage applied on a side gate, a separate n-type doped region, causes an increase in the thickness of the negatively charged layer at the FET channel interface in the substrate, through hole emission from hole traps. The FET channel current is modulated by the electron depletion of the n-type channel, which results from the compensation for the extension of the negatively charged layer at the n-i interface into the i-substrate containing hole traps. The magnitude of the drain current reduction is determined by the total acceptor concentration in the substrate and the donor concentration of the channel. However, the magnitude is independent of the side-gate distances     

AlGaN/GaN heterostructure field-effect transistor model includingthermal effects

A new AlGaN/GaN heterostructure field-effect transistor (HFET) model, in the framework of the gradual channel approximation and based on Monte Carlo simulations of the electron transport properties, is presented. The effects on the dc HFET output characteristics arising from contact resistances, from the ungated access channels between the gate and the source and between the gate and the drain, and from self-heating are analyzed. By examining the channel potential, the ungated regions are shown to have nonlinear characteristics. The solution method uses implicit analytical relationships for the current in the gated and ungated segments of the channel that are connected by matching boundary conditions. Thermal effects on the transport parameters associated with self-heating are included self-consistently. The model results are in very good agreement with experimental data from AlGaN/GaN HFETs fabricated on sapphire substrates. The model also identifies several device design parameters that need to be adjusted to obtain optimized performance in terms of output current and transconductance     

On the effect of bias on the behavior of MOS structures subjected to ionizing radiation

Using a quantitative model [6], the analysis of published data on the effect of the gate bias on the behavior of MOS structure subjected to ionizing radiation is performed. It is shown that, along with hydrogen-containing traps, there are hydrogen-free hole traps in samples with a low content of hydrogen; traps of both types are distributed inhomogeneously over the thickness of the gate insulator. In addition to ionized hydrogen, neutral hydrogen is involved in the formation of surface states and provides the main contribution to this process at negative gate bias. A decrease in the shift of the threshold voltage in the case of high fields is caused by an increase in the drift component of the hole drain to the electrodes.

     

Temperature dependent subthreshold model of long channel GAA MOSFET including localized charges to study variations in its temperature sensitivity

In this paper, degrading effects of hot carrier damage/radiation damage/process damage induced interface localized charges on the temperature sensitivity of the Cylindrical Gate All Around (GAA) MOSFET are investigated. A temperature dependent numerical model is developed for GAA MOSFET including interface localized charges and the results so obtained are validated with the simulation results of ATLAS 3D device simulator. Results show that subthreshold region is the most affected region in both the cases i.e. (1) in presence of localized charges and (2) under temperature variation. Also degrading effects of localized charges are found to be more pronounced at low temperatures. Apart from electrical performance degradation, localized charges change the temperature sensitivity of the device i.e. change in temperature coefficient of the drain current and zero crossover point (gate bias corresponding to zero temperature coefficient).