A monolithic gallium arsenide interval timer IC with integrated PLLclock synthesis having 500-ps single shot resolution

A gallium arsenide (GaAs) integrated circuit for measuring single shot time intervals with 500-ps resolution has been designed, fabricated, and tested. The circuit contains a 12-b counter that can be extended externally and control circuitry for the detection of multiple intervals. Options such as number of intervals, minimum interval time, and timing resolution are user programmable. The circuit employs a self-contained 2.0-GHz phase-locked loop (PLL) clock synthesizer with less than 5 ps rms jitter and a lock time of 2.5 μs. The circuit is packaged in a 14-mm², 52-pin thermally enhanced plastic package and operates from a single +5-V supply. The nominal power dissipation is 2.8 W. The circuit is fabricated in a 0.6-μm gate length, enhancement/depletion GaAs MESFET process utilizing four layers of gold interconnect metallization. Inductors, capacitors, and thin film resistors can be fabricated in this process, enabling integrated analog circuitry. The die size is 3.28 by 3.15 mm. The circuit has applications in collision avoidance sensors, laser rangefinders, surveying, police radar, and test instrumentation     

A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-${rm mu}hbox{m}$ CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of $-$ 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm $times$ 0.95 mm.      

S/U双波段小数分频锁相环型频率合成器设计

提出了一种覆盖S/U双波段的小数分频锁相环型频率合成器.该频率合成器采用一种新型多模分频器,与传统的小数分频频率合成器相比具有稳定速度快、工作频率高和频率分辨率高的优点.该锁相环采用了带有开关电容阵列(SCA)的LC-VCO实现了宽频范围,使用3阶MASH△-∑调制技术进行噪声整形,降低了带内噪声.设计基于TSMC 0.25 μm 2.5 V 1P5M CMOS工艺实现.测试结果表明,频率合成器频率范围达到2.450～3.250 GHz;波段内偏离中心频率10 kHz处的相位噪声低于-92.5 dBc/Hz,1 MHz处的相位噪声达到-120 dBc/Hz;最小频率分辨率为13 Hz;在2.5 V工作电压下,功耗为36 mW.     

A monolithic digital chirp synthesizer chip with I andQ channels

A monolithic digital chirp synthesizer (DCS) chip has been developed using GaAs/AlGaAs HI²L technology. The 6500-HBT-gate DCS chip is capable of producing linear frequency-modulated (chirp) waveforms or single-frequency waveforms. The major components of the DCS are two 28-b pipelined accumulators, a 1.8 kb sine ROM, a 1.8 kb cosine ROM, and two 8 b digital-to-analog converters (DACs). The total chip area is 4.877 mm×6.172 mm using a minimum feature size of 1.5 μm. All components of the DCS are fully functional and the device has been clocked to 450 MHz with a power dissipation of 18 W     

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm².     

High-performance AlGaAs/GaAs SDHTs and ring oscillators grown byMBE on Si substrates

High-performance AlGaAs/GaAs selectively doped heterojunction transistors (SDHTs) and 19-stage oscillators fabricated on silicon substrates are discussed. Epitaxial layers of AlGaAs/GaAs were grown by MBE on Si substrates. The mobility of two-dimensional electron gas (2DEG) in the SDHTs was as high as 53000 cm²/V-s at 77 K for a sheet charge density of 10×1¹² cm^-2. For 1-μm-gate-length devices, maximum transconductances of 220 and 364 mS/mm were measured at 300 and 77 K, respectively, for the SDHTs. A minimum propagation delay time of 27 ps/stage at room temperature was obtained for a 19-stage direct-coupled FET logic ring oscillator with a power dissipation of 1.1 mW/stage. The propagation delay time was reduced to 17.6 ps/stage at 77 K. From microwave S-parameter measurements at 300 K, current gain and power gain cutoff frequencies of 15 and 22 GHz, respectively, were measured. These results are comparable to those obtained for SDHT technology on GaAs substrates     

Hybridized off-line 2-MHz zero-current-switched quasi-resonantconverter

Thick-film hybrid technology is used to develop a half-bridge, half-wave, zero-current-switched quasi-resonant converter for 300 V DC offline application. With a conversion frequency of 2 MHz the converter delivers 80 W at 78% efficiency with a power density, excluding heat sink, of 21 W/in³. The operation and detailed electrical and hybrid design of the circuit are described. Also described is a 2 MHz hybridized gate drive     

A compact DC-to-DC power converter for distributed power processing

The authors present a compact (55-W/in³), efficient (86% power train), 1-MHz switch-mode, DC-to-DC power converter contained in a 2-in by 2-in by 0.25-in, 1-in³ package. They describe the interleaved forward topology, steady-state analysis, switch transitions, capacitor substrate, planar printed-wiring-board transformer, packaging, electrical performance, power loss analysis, thermal analysis, reliability, and efficiency and power density improvements     

High-speed DCFL circuits with very shallow junction GaAs JFETs

High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1×10¹⁸ cm^-3 together with a very shallow junction depth of less than 30 nm for the p⁺-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 μm. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p⁺-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate     

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

W-band divide-by-3 frequency divider using 0.1 /spl mu/m InAlAs/InGaAs metamorphic HEMT technology

A W-band divide-by-3 frequency divider with wide bandwidth and low power dissipation is presented using harmonic injection-locking technique. A cascode FET is employed for a self-oscillating second-harmonic mixer which is injection-locked by third-harmonic input to obtain the division order of three. The fabricated frequency divider using 0.1 /spl mu/m GaAs metamorphic HEMT technology shows superior performance such as large bandwidth of 6.1 GHz around 83.1 GHz (7.3%) under small DC power consumption of 12 mW.     

An 8-b slice GaAs bus logic LSI for a high-speed parallelprocessing system

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7×7-mm² chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8-μm WN_x gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s     

A high-speed and highly uniform submicrometer-gate BPLDD GaAsMESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V_th uniformity, and FET operating speed, simultaneously. For 0.7-μm gates, a Mg⁺ dose of 2×10¹² cm^-2 at 300 keV and a Si⁺ dose of 2×10¹² cm^-2 at 50 keV are suitable for the p layer and n' layer, respectively. A σV _th of 7 mV is realized. Gate-edge capacitance of the 0.7-μm-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/μm, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7-μm-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern     

Submicrometer n+-Ge gate AlGaAs/GaAs MISFETs

Submicrometer n⁺-Ge gate AlGaAs/GaAs MISFETs have been developed by designing a fabrication process for the n⁺-implanted region. The short-channel effect was sufficiently suppressed by lowering the ion-implantation energy down to 50 keV to achieve a standard deviation of threshold voltage as small as 13 mV for 0.5-μm-gate FETs in a 2-in-diameter wafer. The source resistance was reduced by increasing the annealing temperature to 850°C to obtain a transconductance of 500 mS/mm for a 0.5-μm-gate FET. Even after annealing at such a high temperature, the quality of the channel layer was maintained at a sufficient level to realize a large cutoff frequency of 70 GHz for a 0.4-μm-gate FET. A divide-by-four static frequency divider was also fabricated using the above-mentioned fabrication technology. Successful operation at 16 GHz at 300 K was obtained with a divider using 0.9-μm-gate FETs at a low power dissipation of 36 mW per T-flip-flop     

Nanoscale modification of phase change materials with near-field light

Scanning near-field optical microscope (SNOM) was applied to the formation of ultrasmall phase change domains to investigate the feasibility of ultrahigh density data storage. Phase change domains ranging 60 – 100 nm in diameter, which is far beyond the diffraction limit, could be successfully written in amorphous GeSbTe recording film by point heating with pulsed laser light (λ=785 nm, 7 mW, 0.5 ms) through the optical fiber probe whose aperture size was nearly 50 – 100 nm. The detected power in observation of these recorded domains is 10² – 10³ times as high as that in magneto-optical observation. It indicates that phase change recording with SNOM has a potential to achieve ultrahigh density data storage (more than 100 Gb/in²) with high signal detection efficiency.     

A WNxgate self-aligned GaAs p-channel MESFET for complementary logic

The Schottky barrier of reactively sputtered WNxto p-type GaAs has been investigated. Postdeposition heat treatments above 500°C led to a reduction in the barrier height but for lamp annealing at 740°C the barrier heights are 0.68 eV. Self-aligned p-channel MESFET's were fabricated with WNxgates by a refractory metal process involving the above heat treatment. The Schottky-barrier heights were close to the expected values. K-values of FET's with 2 µm × 24 µm gates were 0.088 mA/V², consistent with previously reported results. SPICE simulation studies carried out for a variety of complementary-type logic gates, indicate that power dissipation × delay time products of less than 10 fJ may be achievable over the power range 5-50 µW/gate. Thus complementary logic may be useful for applications where low power dissipation is at a premium.     

Effect of height on power density in spiral-wound power-pot-coretransformers

The effect of height on power density in spiral-wound power-pot-core transformers is examined for the practical range of power, frequency, loss, and volt-per-turn. Relevant mechanical and electrical equations are derived and applied to an optimization algorithm that searches for the design that maximizes the power density at a given height. It has been found that the curves of power density versus height exhibit a peak (on the order of 1000 W/in³ in several cases) at a critical height between 0.25 and 0.3 in. Below this critical height, the power density decreases drastically     

A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm², and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power     

20 W CW surface emitting 0.8 μm GaAs/GaAlAs laser diodes

A continuous-wave optical power density of 200 W/cm² is reported for the first time for a 0.1 cm² element of a surface emitting GaAs/GaAlAs wafer. The laser facets are cleaved on-wafer by a microcleavage technique. The output optical beam is reflected by 45°-integrated beam deflectors situated at a distance of 15 μm from each laser facet. The lasers were soldered junction-up on a microchannel CuW cooler. The drive current at 20 W CW is 40 A with a slope efficiency of 0.7 W/A     

High-speed small-scale InGaP/GaAs HBT technology and itsapplication to integrated circuits

We have developed the advanced performance, small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) by using WSi/Ti base electrode and buried SiO₂ in the extrinsic collector. The base-collector capacitance C_BC was further reduced to improve high-frequency performance. Improving the uniformity of the buried SiO ₂, reducing the area of the base electrode, and optimizing the width of the base-contact enabled us to reduce the parasitic capacitance in the buried SiO₂ region by 50% compared to our previous devices. The cutoff frequency f_T of 156 GHz and the maximum oscillation frequency f_max of 255 GHz were obtained at a collector current I_C of 3.5 mA for the HBT with an emitter size S_E of 0.5×4.5 μm², and f_T of 114 GHz and f_max of 230 GHz were obtained at I_C of 0.9 mA for the HBT with S_E of 0.25×1.5 μm². We have also fabricated digital and analog circuits using these HBTs. A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed, low-power circuit applications