Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing (TDM) scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency.     

A 9‐Bit 80‐MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique

A 9‐bit 80‐MS/s CMOS pipelined folding analog‐to‐digital converter employing offset‐canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc‐decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ×0.6 LSB and ×1.6 LSB, respectively.     

Test Scheduling of NoC‐Based SoCs Using Multiple Test Clocks

Network‐on‐chip (NoC) is an emerging design paradigm intended to cope with future systems‐on‐chips (SoCs) containing numerous built‐in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC‐based SoCs. Among the existing test issues for NoC‐based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC‐based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC‐based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC‐based SoCs.     

A self-timed divider using a new fast and robust pipeline scheme

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)     

Wi‐Fi‐based modeling and hybrid routing scheme for delay‐tolerant public bus network

Delay‐ or Disruption‐Tolerant Networking (DTN) is a communications approach that is utilized in easily disrupted or delayed networks. Examples of such networks are often found in heterogeneous networks, mobile or extreme terrestrial networks, and planned networks in space. In this paper, we examine the metropolitan bus network as a research target of DTN for a public transport network. We analyze the metropolitan bus network through spatial and temporal modeling using an existing Bus Information System (BIS) database. On the basis of the results of our analysis, we propose and design an appropriate DTN routing scheme called Hybrid Position‐based DTN Routing. This scheme uses position‐based routing instead of address‐based routing by soliciting infrastructural help from nearby Access Points for the real‐time BIS location service. We simulated our scheme using a WLAN for the wideband DTN communication and evaluated it by comparing it with traditional Ad hoc flooding, Epidemic routing, and strategic protocol steps in our own algorithm. The results indicate that our scheme achieves reasonably high performance in terms of packet delivery ratio, latency, and resource usage. Copyright © 2013 John Wiley & Sons, Ltd.     

Applying CDMA Technique to Network-on-Chip

The issues of applying the code-division multiple access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A packet switched network-on-chip (NoC) that applies the CDMA technique is realized in register-transfer level (RTL) using VHDL. The realized CDMA NoC supports the globally-asynchronous locally-synchronous (GALS) communication scheme by applying both synchronous and asynchronous designs. In a packet switched NoC, which applies a point-to-point connection scheme, e.g., a ring topology NoC, data transfer latency varies largely if the packets are transferred to different destinations or to the same destination through different routes in the network. The CDMA NoC can eliminate the data transfer latency variations by sharing the data communication media among multiple users concurrently. A six-node GALS CDMA on-chip network is modeled and simulated. The characteristics of the CDMA NoC are examined by comparing them with the characteristics of an on-chip bidirectional ring topology network. The simulation results reveal that the data transfer latency in the CDMA NoC is a constant value for a certain length of packet and is equivalent to the best case data transfer latency in the bidirectional ring network when data path width is set to 32 bits.     

Circuit‐based logical layer 2 bridging in software‐defined data center networking

With the expansion of the size of data centers, software‐defined networking (SDN) is becoming a trend for simplifying the data center network management with central and flexible flow control. To achieve L2 abstractions in a multitenant cloud, Open vSwitch (OVS) is commonly used to build overlay tunnels (eg, Virtual eXtensible Local Area Network [VXLAN]) on top of existing underlying networks. However, the poor VXLAN performance of OVS is of huge concern. Instead of solving the performance issues of OVS, in this paper, we proposed a circuit‐based logical layer 2 bridging mechanism (CBL2), which builds label‐switched circuits and performs data‐plane multicasting in a software‐defined leaf‐spine fabric to achieve scalable L2 without overlay tunneling. Our evaluations indicate that direct transmission in OVS improves throughput performance by 58% compared with VXLAN tunneling, and data‐plane multicasting for ARP reduces address resolution latency from 149 to 0.5 ms, compared with control‐plane broadcast forwarding. The evaluation results also show that CBL2 provides 0.6, 0.4, and 11‐ms protection switching time, respectively, in the presence of switch failure, link failure, and port shutdown in practical deployment.     

The “packing” and the “scheduling packet”switch architectures for almost all-optical lossless networks

This paper proposes two almost all-optical packet switch architectures, called the “packing switch” and the “scheduling switch” architecture, which when combined with appropriate wait-for-reservation or tell-and-go connection and how control protocols provide lossless communication for traffic that satisfies certain smoothness properties. Both switch architectures preserve the order of packets that use a given input-output pair, and are consistent with virtual circuit switching, The scheduling switch requires 2klogT+k² two-state elementary switches (or 2klogT+2klogk elementary switches, if a different version is used) where k is the number of inputs and T is a parameter that measures the allowed burstiness of the traffic. The packing switch requires very little processing of the packet header, and uses k²logT+klogk two-state switches. We also examine the suitability of the proposed architectures for the design of circuit switched networks. We find that the scheduling switch combines low hardware cost with little processing requirements at the nodes, and is an attractive architecture for both packet-switched and circuit-switched high-speed networks     

基于网络监控器的专用片上网络动态容错路由

针对专用片上网络（Network on Chip,NoC）全局通信事务管理和可靠性设计问题,提出片上网络监控器的概念,用于获取全局网络实时状态信息及执行路径分配算法,基于此提出一种动态路由机制DyRS-NM.该机制能检测和定位NoC中的拥塞和故障链路,并能区分瞬时和永久性链路故障,采用重传方式避免瞬时故障,通过重新路由计算绕开拥塞和永久性故障.设计实现了RTL级网络监控器和与之通信的容错路由器模块,并将MPEG4解码器应用映射至基于网络监控器的4×4Mesh结构NoC体系结构中,验证了系统性能以及面积功耗开销.相比静态XY路由和容错动态路由FADR,DyRS-NM机制在可接受的开销代价下获得了更优的性能.     

A Low Power Analog CMOS Vision Chip for Edge Detection Using Electronic Switches

An analog CMOS vision chip for edge detection with power consumption below 20 mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts: one is a logarithmic compression photocircuit, and the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is off, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with 128 × 128 pixels, was below 20 mW. The vision chip was designed using 0.25 µm 1‐poly 5‐metal standard full custom CMOS process technology.     

Retina‐Motivated CMOS Vision Chip Based on Column Parallel Architecture and Switch‐Selective Resistive Network

A bio‐inspired vision chip for edge detection was fabricated using 0.35 μm double‐poly four‐metal complementary metal‐oxide‐semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of 160×120 pixels has been fabricated in 5×5 mm² silicon die. It shows less than 10 mW of power consumption.     

Automated optimization for memory‐efficient high‐performance deep neural network accelerators

The increasing size and complexity of deep neural networks (DNNs) necessitate the development of efficient high‐performance accelerators. An efficient memory structure and operating scheme provide an intuitive solution for high‐performance accelerators along with dataflow control. Furthermore, the processing of various neural networks (NNs) requires a flexible memory architecture, programmable control scheme, and automated optimizations. We first propose an efficient architecture with flexibility while operating at a high frequency despite the large memory and PE‐array sizes. We then improve the efficiency and usability of our architecture by automating the optimization algorithm. The experimental results show that the architecture increases the data reuse; a diagonal write path improves the performance by 1.44× on average across a wide range of NNs. The automated optimizations significantly enhance the performance from 3.8× to 14.79× and further provide usability. Therefore, automating the optimization as well as designing an efficient architecture is critical to realizing high‐performance DNN accelerators.     

Performance Analysis for MPEG‐4 Video Codec Based on On‐Chip Network

In this paper, we present a performance analysis for an MPEG‐4 video codec based on the on‐chip network communication architecture. The existing on‐chip buses of system‐on‐a‐chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on‐chip network is introduced to solve the problem of on‐chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG‐4 video codec based on the on‐chip network and Advanced Micro‐controller Bus Architecture (AMBA) on‐chip bus. Experimental results show that the performance of the MPEG‐4 video codec based on the on‐chip network is improved over 50% compared to the design based on a multi‐layer AMBA bus.     

Outage analysis of opportunistic‐based hybrid decode‐amplify‐forward relaying in polar code environment

Outage analysis plays a vital role in wireless systems to determine reliable transmission and effective communication. Incremental hybrid decode‐amplify‐forward (IHDAF) relay offers a way of meeting the challenges of capacity and coverage improvement with great potential in cooperative communication networks. Therefore, opportunistic incremental hybrid relaying must be integrated with coding schemes to achieve full diversity. In this paper, the outage behavior of polar coded and distributed coded cooperative relaying schemes is analyzed. Simulation results show that opportunistic incremental HDAF using polar code offers an outage capacity of 17 b/s/Hz for 4 × 4 multiantenna and 45 b/s/Hz in 8 × 8 multiantenna systems with an outage of 10^?8 and 10^?13, respectively. Moreover, the polar coded opportunistic IHDAF system in 8 × 8 MIMO achieves 2 and 6 dB higher gains compared with amplify‐and‐forward (AF) and decode‐and‐forward (DF) relaying schemes. The closed‐form expression for outage probability has been derived through Marcum‐Q approximations and processed through Monte Carlo simulations.     

片上网络拓扑结构的研究

随着SoC体系结构设计复杂度的提高,传统的总线结构已成为IP核之间通信的瓶颈。为了满足大规模集成电路发展对扩展性、能耗、面积、时钟异步、重用性、QoS等方面的需求,新的设计方法—片上网络(NoC)应运而生,它是对原有设计模式的一次革新。本文分析了NoC的技术特点以及在该领域中的关键技术,详细地对NoC中常见的拓扑结构进行了分类研究,并指出了每种拓扑结构中的优点与不足;然后通过分析每种拓扑结构的性能参数,从而对其性能进行综合的比较。     

Application-aware virtual paths insertion for NOCs

Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.     

NoC:下一代集成电路主流设计技术

从SoC的定义出发,依据“PC参考系准则”、“十年变革规律”、“半导体技术发展规律”等基本规律,提出并论证了“NoC是下一代集成电路主流设计技术”的观点,概括了NoC基础理论体系的主要研究领域;简要分析了集成电路NoC体系结构领域可能的关键技术。NoC技术从体系结构上彻底解决了SoC的总线结构所固有的三大问题:由于地址空间有限而引起的扩展性问题,由于分时通讯而引起的通讯效率问题,以及由于全局同步而引起的功耗和面积问题。     

Improving the reliability of Byzantine fault‐tolerant distributed software‐defined networks

This paper presents a method to improve the reliability and fault tolerance of distributed software‐defined networks. This method is called “BIRDSDN (Byzantine‐Resilient Improved Reliable Distributed Software‐Defined Networks).” In BIRDSDN, a group communication is implemented among the controllers of the whole clusters. This method can detect the crash failure and Byzantine failure of any controller and undertakes a fast detection and recovery scheme to select the controllers to take over the orphan switches. BIRDSDN takes into account the reliability of the nodes considering the failure probability of intracluster and intercluster links, topology, load, and latency. The numerical results show that this approach performs better than the other approaches regarding failure detection, recovery, latency, throughput, reliability, and packet loss.     

Design and implementation of a scalable switch architecture for efficient high‐speed data multicasting

This paper presents the design and implementation of a new scalable cell‐based multicast switch fabric for broadband communications. Using distributed control and modular design, the multicast balanced gamma switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non‐uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switch element with the self‐routing and contention resolution functions. Thus, no dedicated copy network is required. In the paper, we discuss in detail the design issues associated with the multicast functionality of the switch using 0.18 µm CMOS technology and discuss the scalability of the switch in terms of architectural, implementation, and performance scalability. Synthesized results are provided for measures of circuit complexity and timing. Copyright © 2006 John Wiley & Sons, Ltd.     

A 160×120 Light‐Adaptive CMOS Vision Chip for Edge Detection Based on a Retinal Structure Using a Saturating Resistive Network

We designed and fabricated a vision chip for edge detection with a 160×120 pixel array by using 0.35 µm standard complementary metal‐oxide‐semiconductor (CMOS) technology. The designed vision chip is based on a retinal structure with a resistive network to improve the speed of operation. To improve the quality of final edge images, we applied a saturating resistive circuit to the resistive network. The light‐adaptation mechanism of the edge detection circuit was quantitatively analyzed using a simple model of the saturating resistive element. To verify improvement, we compared the simulation results of the proposed circuit to the results of previous circuits.