宏单元模式分级布图规划方法

本文提出一个新的宏单元模式分级布图规划方法.布图规划分三个阶段进行:芯片物理分级构造、布图规划和布图规划修正.主要特点包括:松弛对布图拓扑结构的约束、模块“自然”结群构造设计物理分级、采用解析方法求解面积规划问题、基于一个新的Steiner树算法求布线规划、包含模块面积估计和布线面积估计.实验结果表明提出的方法可以在满足不同形状和I/O设计目标的同时得到很高的芯片面积利用率.     

片上网络拓朴优化:在离散平面上布局与布线

微系统芯片(System-on-Chip,SoC)发展到今天,集成密度指数增长和芯片面积的急剧膨胀使得全局连线的延时上升,可靠性下降,成为集成电路的设计瓶颈.片上网络(Network-on-Chip,NoC)是解决整个芯片上数据有效传输的结构之一,以片上网络为基础通信架构的微系统芯片称为片上网上系统芯片(System-on-Network-on-Chip,SoNoC).微系统芯片内通信模式兼有随机性和确定性,应该根据特定应用的通信特征设计片上网络.本文在确定SoNoC设计流程的基础上,根据SoNoC的通信特征,选择了合适的离散平面结构,对SoNoC的运算及控制等模块进行布局、对模块间的通信依赖关系进行布线,发展出FRoD(Floor-plan and Routing on Discrete Plane)算法,以自动生成片上网络的拓扑结构.该算法定义了离散平面的一般表示方法,并在四种典型的离散平面上使用不同规模的随机系统完成了系列实验.为了处理系统和网络之间的耦合关系,逐点分裂的布局算法可以逐步学习和适应系统的通信需求,同时优化系统的执行时间和通信能量,在运行随机任务流图的模拟系统上与随机布局结果相比可以节省30%左右的通信能量,20%左右的系统通信时间.串行、并行和串并混合的布线算法使用最短路径把通信关系分布在离散平面的通道上,使不同的通信关系尽量复用网络通道,与全连接网络相比可以节省10%到30%的面积代价.     

一种带权动态调整的总体布线算法及其实现

本文对现有的总体布线方法及宏单元阵列总体布线问题进行了详细分析,提出了一种基于带权动态调整思想的适合于宏单元阵列一层半和双层版图模式的总体布线算法,其目标是合理地利用已确定的布线区域,使各线网均匀地分布在芯片上,获得尽可能高的布通率。     

BBL布局调整的极图模型

<正> BBL的布局问题已作过许多研究,但很多布局方法对结果缺乏预计,使最终布局与便利于布线的目标不一定吻合,因而布局调整已成为布局设计中的一种重要手段。本文提出了一种基于极图分解的布局调整方法,分解后的无向(可标向)边代表积木块之间的对角瓶颈,其中走线所占的空间以边权重值来表示;四边瓶颈的大小以有向边(固定标向边)的权重表示。极图分解是在原来Floor—P1an图的基础上进行的。由初始布局得到Floor—P1an图,图中每一条边均表示两个矩形区域相邻的边界,这条边的长度⊿_(iJ),也即这两个区域(记为     

一种模拟“退火”的二维总体压缩算法

在集成电路版图设计中,对积木块模式布图进行总体压缩,可以改善最终布图的质量,然而,二维的总体压缩是个非常复杂与困难的问题。本文设计并实现了一个模拟退火的二维总体压缩算法,并且对它采取了一系列技术措施,使得它的算法复杂度可以接受。本文不仅提出了关于“布线区布线密度函数”的概念以准确地描述当布局移动时布线区动态的布线密度,而且通过使用密度函数保持约束图与动态布局之间的一致性。此外,还提出了将“均匀分布空闲空间”作为总体压缩的优化目标之一,以使得由于布线区布线容量不足而引起的溢出大大地减少了,并且优化过程的效率也将提高。实例表明,本算法既实用又有效。     

微电子学、集成电路

TN42007060826适于数模混合集成电路的可布性分析模型/李桢荣,刘晓彦,张锡盛(北京大学深圳研究生院)//北京大学学报(自然科学版).―2007,43(1).―61～66.布局、布线是集成电路后端物理设计的两个主要环节,可布性分析作为连接布局和布线的枢纽,对优化布局和提高布线的布通率具有非常重要的作用。作者提出一种不可切割(non-slicing)结构的非均匀划分算法,大幅度减少了划分后的区域数量,同时建立了与此相应的适用于数模混合集成电路布局的可布性分析模型。对于实验电路的分析证实了该模型的准确性和高效性。图6表1参11TN42007060827芯片功能…     

用于宏单元阵列的自动布局算法

本文针对宏单元阵列的特点,提出了构造布局和布局改善同时进行的布局算法和以布局均匀和信号网分布均匀为主要目标的多目标布局评价函数.它在布局过程中就考虑到布局对布线的影响,并自始至终地把总体布线的思想恰如其份地和布局问题结合起来.另外,比以在的算法增加了以局部区域通道布线密度下降为目标的通道布线密度均匀化处理,从而极大地减少了由于局部区域拥挤而造成整个布图失败的可能性.实用结果表明该算法的布局效果是良好的.     

基于角模块布图表示的增量式布图规划算法

提出了一种基于CBL布图表示的新的增量式布图规划算法.该算法能很好地解决包括不可二划分结构在内的布图规划问题.针对现有增量式的一些需求,算法给出了相应的高速解决方案.在已有的初始布局的基础上,基于CBL表示方法建立水平约束和垂直约束图,利用图中关键路径和各模块之间的累加的距离松弛量进行增量式操作.对于新模块的插入,在力求面积最小,线长最短和移动模块数目最少的目标指引下能快速地找到最佳位置作为插入点,高效地完成相关操作,算法的时间复杂性仅为O(n).通过对一组来自工业界的设计实例的测试结果表明,该算法在保证芯片的面积、线长等性能不降低甚至有所改善的情况下,运行速度相当快,仅在μs量级,满足了工业界对增量式布图规划算法在速度上的首要要求,同时保证了基本性能的稳定.     

An Incremental Algorithm for Non-Slicing Floorplan Based on Corner Block List Representation

提出了一种基于CBL布图表示的新的增量式布图规划算法.该算法能很好地解决包括不可二划分结构在内的布图规划问题.针对现有增量式的一些需求,算法给出了相应的高速解决方案.在已有的初始布局的基础上,基于CBL表示方法建立水平约束和垂直约束图,利用图中关键路径和各模块之间的累加的距离松弛量进行增量式操作.对于新模块的插入,在力求面积最小,线长最短和移动模块数目最少的目标指引下能快速地找到最佳位置作为插入点,高效地完成相关操作,算法的时间复杂性仅为O(n).通过对一组来自工业界的设计实例的测试结果表明,该算法在保证芯片的面积、线长等性能不降低甚至有所改善的情况下,运行速度相当快,仅在μs量级,满足了工业界对增量式布图规划算法在速度上的首要要求,同时保证了基本性能的稳定.     

VLSI积木块布图设计的通道定序与布线

本文研究了VLSI积木块布图设计中的通道定序与布线问题。首先提出了T形约束图的概念和通道分级的思想,针对布局中出现的循环通道约束,基于三边通道的布线,通过引入一类通道——预定通道来破坏约束环。在此基础上,给出了一个在给定积木块的布局和总体布线条件下通道定序与布线的有效算法。算法已在UNIVAC1100/10上用FORTRAN77实现,结果令人满意。     

Built-in self-test of global interconnects of field programmable analog arrays

Strategies for the test of Field Programmable Analog Arrays (FPAAs) have been devised based on testing separately their main three components: configurable analog blocks, I/O pads and interconnection network. In this work, a scheme for testing the interconnection network, in particular the global wiring, is presented. As long as analog wiring is considered, catastrophic faults at the switches and wires are considered, as well as parametric capacitive or resistive defects in interconnects. Similarly to FPGAs, critical path search is based on a graph model, so that known algorithms are reused, yielding a minimum number of Test Configurations. Then, a near-zero area overhead BIST procedure is proposed, in which Analog Built-in Block Observers are implemented as oscillators and integrators, respectively, generating test stimuli and analyzing output responses, using internal configurable resources of the FPAA.     

基于图卷积的视网膜血管轮廓及高不确定度区域细化框架

针对传统卷积神经网络(convolutional neural network, CNN)受感受野大小的限制,无法直接有效地获取空间结构及全局语义等关键信息,导致宽血管边界及毛细血管区域特征提取困难,造成视网膜血管分割表现不佳的问题,提出一种基于图卷积的视网膜血管分割细化框架。该框架通过轮廓提取及不确定分析方法,选取CNN粗分割结果中潜在的误分割区域,并结合其提取的特征信息构造出合适的图数据,送入残差图卷积网络(residual graph convolutional network, Res-GCN)二次分类,得到视网膜血管细化分割结果。该框架可以作为一个即插即用模块接入任意视网膜血管分割网络的末端,具有高移植性和易用性的特点。实验分别选用U型网络(U-neural network, U-Net)及其代表性改进网络DenseU-Net和AttU-Net作为基准网络,在DRIVE、STARE和CHASEDB1数据集上进行测试,本文框架的Sp分别为98.28%、99.10%和99.04%,Pr分别为87.97%、88.87%和90.25%,证明其具有提升基准网络分割效果的细化能力。     

Global interconnect design in a three-dimensional system-on-a-chip

A stochastic model for the global net-length distribution of a three-dimensional system-on-a-chip (3D-SoC) is derived. Using the results of this model, a global interconnect design window for a 3D-SoC is established by evaluating the constraints of: 1) wiring area; 2) clock wiring bandwidth; and 3) crosstalk noise. This window elucidates the optimum 3D-SoC global interconnect parameters for minimum pitch, minimum aspect ratio, and maximum clock frequency. In comparison to a two-dimensional system-on-a-chip (2D-SoC), the design window expands for a 3D-SoC to allow greater flexibility of interconnect parameters, thus increasing the guardbands to process variations. In addition, the limit on the maximum global clock frequency is revealed to increase as S/sup 2/, where S is the number of strata. This increase in on-chip signaling rate, however, comes at the expense of I/O density, highlighting the need for new high-density-I/O packaging techniques to exploit the full potential of 3D-SoC.     

Yield enhancement effects of boosted dual word-line (BDWL) schemefor high density DRAMs

This paper describes the yield enhancement effects of a boosted dual word-line (BDWL) scheme for the first Al wiring in high density DRAMs, with a defect density model and a yield model used for comparison with that of the commonly used word-shunt (WS) scheme. Additionally, the yield of first Al wiring with a step height between memory cell array and peripheral circuit regions is also estimated. The yield estimation demonstrated that the yield enhancement effect of the wide first Al wiring for the BDWL scheme was comparable with or surpassed that of the redundancy for the WS scheme yield, when the first Al wiring pitch over the memory cell array or a BDWL scheme was over 4 times wider than that of the WS scheme. The yield estimation with step height indicated that the first Al wiring yield of the BDWL scheme with the step height exceeded that of the WS scheme with the step height of zero, even if using some global planarization technology     

基于粗精交互融合和迭代图割的舰船可见光图像分割方法

在深入分析典型图割算法的基础上,提出了一种基于粗精交互融合和迭代图割的舰船可见光图像分割方法,主要包括矩形包围盒式的粗交互、基于高斯混合模型的迭代图割、多边形编辑式的精交互和窄带区域内的图割优化。仿真结果表明,本文方法基本达到了预期目标,交互少、分割效果好,可满足后续特征提取和目标识别的需求。     

A study on bipolar VLSI gate-arrays assuming four layers of metal

Describes a design study on a bipolar gate-array or masterslice chip with almost 10000 circuits. It assumes 2.5 /spl mu/m groundrules and four layers of metal, i.e. three layers of metal for global wiring and one layer for power and I/O redistribution. It is proven by using actual logic from the IBM 4331 system, that an additional wiring layer increases the circuit density on a masterslice chip by more than a factor of 2. The paper is divided into three sections. Section 1 describes the chip design, the detailed arrangement of internal and external cells with the associated wiring channels and some general aspects of a masterslice design. Section II explains the placement and wiring tools and gives detailed results of a wiring study, comparing a logic design with 2 wiring layers with the same logic implemented with 3 wiring layers (4 layers total). Section III covers the off-chip communication with its associated problems like noise generation by simultaneous driver switching, three-state driver, and embedded RAM macro testing.     

改进GCNs在指静脉特征表达中的应用

基于图模型的指静脉全局特征表达方法不仅可以降低成像质量对采集设备的依赖性,还能提高匹配效率。针对于目前指静脉图模型的研究中存在的图结构不稳定,匹配效率随图模型的变大而降低的问题,本文提出了一种基于SLIC(Simple Linear Iterative Clustering)超像素分割算法构建加权图的方法,并改进ChebyNet图卷积神经网络(Graph Convolutional Neural Networks, GCNs)提取加权图的图级(graph-level)特征。针对指静脉样本数普遍较少,而ChebyNet中卷积网络参数量较大容易造成过拟合以及其快速池化层不能自适应地选择节点的问题,本文提出了全局池化结构的改进GCNs模型SCheby-MgPool(Simplified Cheby-Multi gPool)。实验结果表明,本文提出的方法提取的指静脉特征在识别精度,匹配效率上都具有较好的性能。      

Component placement through graph partitioning in computer-aided printed-wiring-board design

The partitioning of the abstract graph representing an electronic circuit has been applied to the placement of components on a printed wiring board. Results obtained from a computer program exhibit a marked degree of similarity to placements produced by a skilled draughtsman, for a very low processing cost.     

Global relational reasoning with spatial temporal graph interaction networks for skeleton-based action recognition

With the prevalence of accessible depth sensors, dynamic skeletons have attracted much attention as a robust modality for action recognition. Convolutional neural networks (CNNs) excel at modeling local relations within local receptive fields and are typically inefficient at capturing global relations. In this article, we first view the dynamic skeletons as a spatio-temporal graph (STG) and then learn the localized correlated features that generate the embedded nodes of the STG by message passing. To better extract global relational information, a novel model called spatial–temporal graph interaction networks (STG-INs) is proposed, which perform long-range temporal modeling of human body parts. In this model, human body parts are mapped to an interaction space where graph-based reasoning can be efficiently implemented via a graph convolutional network (GCN). After reasoning, global relation-aware features are distributed back to the embedded nodes of the STG. To evaluate our model, we conduct extensive experiments on three large-scale datasets. The experimental results demonstrate the effectiveness of our proposed model, which achieves the state-of-the-art performance.