Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Die separation and packaging of a surface micromachined piezoresistive pressure sensor

The processing steps required to obtain a useful single medical sensor assembly are discussed, starting from an entire silicon wafer with thousands of surface micromachined sensors. Experiences concerning dicing and packaging of a piezoresistive pressure sensor are described, together with proposals for solutions. Problems with fracture of essential sensor structures are solved by use of a wafer protection tape. Existing solutions for flip–chip bonding and design of substrate for electrical interconnection are pushed to their limits due to the very small size of the novel sensor. As many of the processes can be simplified by an improved MEMS design, critical points related to the design are addressed.     

Novel combined through-wafer-groove fabrication approach and its application in wafer level packaging of GaAs CCD

This paper presents a novel combined through-wafer-groove fabrication approach, which is applied to the wafer level packaging (WLP) of GaAs charge coupled devices (CCD) for electrical interconnection. The combined methodology includes mechanical dicing of the groove and wet chemical etching for polishing. The parameters of the mechanical dicing are researched, including feed speed, dicing directions of the wafer, and cutting depth, to minimize the chipping. Two kinds of chemical solution are tried, and the results are discussed. Besides, the etch rate is measured, which provides a guideline for the process design. Finally, GaAs-CCD WLP sample is achieved and the electrical properties are tested to validate the feasibility of this fabrication approach. This methodology is featured by low cost, low process temperature, and good process uniformity.     

Stereolithography on silicon for microfluidics and microsensor packaging

 Stereolithography can be used to fabricate 3-D and high aspect ratio microstructures with low manufacturing cost and short fabrication time. Stereo lithography can customize the packages for microfluidics and microsensors to eliminate the dead volume of the reaction chamber. Fabrication of MEMS packages on a wafer level scale can decrease the manufacturing time and assembly time. In order to show the feasibility of integration of stereolithography with micromachined devices, alignment, cleaning, and dicing tests have been investigated. Stereolithography was applied to chemical sensors, interdigitated electrodes, and an AFM cantilever fluid cell package. After the cleaning process the devices were tested and passed a functional test. Received: 10 August 2001/Accepted: 24 September 2001 This project was supported by G. W. Woodruff School of Mechanical Engineering. Rapid Prototyping Manufacturing Institute and Microelectronic Research Center sponsored the experiment apparatus. Authors would like to thank Dr. James Gole and Lenward Seals for the test of the packaged chemical sensors, the help from Stan Halpern for dicing the wafer to individual measurement. Finally, authors would like to thank the helps from the MEMS research laboratory at Georgia Tech. This paper was presented at the Fourth International Workshop on High Aspect Ratio Microstructure Technology HARMST 2001 in June 2001.     

Reticle Design for Minimizing Multiproject Wafer Production Cost

Multiproject wafer (MPW) production cost is sensitive to how the chips are arranged in a reticle. In this paper, we propose a methodology for exploring the reticle floorplan design space to minimize MPW production cost. Experimental results show that our methodology often achieves double-digit cost savings. A study using MPW for volume production shows that the volume cutoff points range from a few thousand dice to tens of thousands of dice. Note to Practitioners-This paper proposes a methodology for minimizing MPW production cost via better chip placement in a reticle (called reticle floorplanning). Our methodology consists of an effective reticle floorplanning method, two simulated wafer dicing methods, two cost estimation models, and a procedure for calculating the cost assumed by each project. A design service company or a foundry can use our methodology to reduce MPW production cost and, thus, provides a more affordable and expedient service to its customers. The reticle floorplanning method and simulated wafer dicing methods employed here are the state-of-the-art. A practitioner should adapt these methods to other MPW problems such as dealing with multitechnology process, placing multiple instances of the same design in a reticle, etc. The cost models should also be revised accordingly. The cost data given in this paper should be used only for reference as mask tooling and wafer fabrication costs constantly change. The cost model proposed for calculating the production cost assumed by each project can serve as a basis for developing a fairer pricing model. The study of using MPW for low to medium-volume production is also very useful. It may help a customer deliver its product earlier to market using a low-cost fabrication program. The problem addressed in this paper becomes much simpler if the side-to-side wafer dicing constraint is removed.     

Chirality assignment to carbon nanotubes integrated in MEMS by tilted-view transmission electron microscopy

Front side etching combined with sample tilting - instead of wafer through etching - allows for transmission electron microscopy (TEM) investigations on nanostructures integrated in microelectromechanical systems (MEMS). We present electron diffraction of an individual single-walled carbon nanotube (SWNT) suspended between sharp polycrystalline silicon tips as far as 165 μm away from the MEMS chip edge. This novel approach for transmission-beam characterization avoids complex wafer backside processing and facilitates alignment of the SWNTs to the focal plane using tips defined directly by photolithographic means. The demonstration of chirality assignment to the integrated SWNT paves the way for correlating experimentally measured response of the SWNT sensing element upon stimuli with the response predicted by theory.     

基于圆片级阳极键合封装的高g_n值压阻式微加速度计

设计了一种适合于高gn值压阻式微加速度计圆片级封装的结构,解决了芯片制造工艺过程中电极通道建立、焊盘保护、精确划片等关键技术。采用玻璃—硅—玻璃三层阳极键合的方式进行圆片级封装,较好地解决了芯片密封性、小型化和批量化等生产难题。在4 in生产线上制作的高gn值压阻式微加速度计样品,尺寸仅为1 mm×1 mm×0.8 mm;对传感器进行的校准与抗冲击性能测试,结果表明:样品具备105gn的抗冲击能力、0.15μV/gn/V的灵敏度以及200 kHz的谐振频率。     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.     

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

M-TEST: A test chip for MEMS material property measurement usingelectrostatically actuated test structures

A set of electrostatically actuated microelectromechanical test structures is presented that meets the emerging need for microelectromechanical systems (MEMS) process monitoring and material property measurement at the wafer level during both process development and manufacturing. When implemented as a test chip or drop-in pattern for MEMS processes, M-Test becomes analogous to the electrical MOSFET test structures (often called E-Test) used for extraction of MOS device parameters. The principle of M-Test is the electrostatic pull-in of three sets of test structures [cantilever beams (CB's), fixed-fixed beams (FB's), and clamped circular diaphragms (CD's)] followed by the extraction of two intermediate quantities (the S and B parameters) that depend on the product of material properties and test structure geometry. The S and B parameters give a direct measure of the process uniformity across an individual wafer and process repeatability between wafers and lots. The extraction of material properties (e.g., Young's modulus, plate modulus, and residual stress) from these S and B parameters is then accomplished using geometric metrology data. Experimental demonstration of M-Test is presented using results from MIT's dielectrically isolated wafer-bonded silicon process. This yielded silicon plate modulus results which agreed with literature values to within ±4%. Guidelines for adapting the method to other MEMS process technologies are presented     

Robust design and model validation of nonlinear compliant micromechanisms

Although the use of compliance or elastic flexibility in microelectromechanical systems (MEMS) helps eliminate friction, wear, and backlash, compliant MEMS are known to be sensitive to variations in material properties and feature geometry, resulting in large uncertainties in performance. This paper proposes an approach for design stage uncertainty analysis, model validation, and robust optimization of nonlinear MEMS to account for critical process uncertainties including residual stress, layer thicknesses, edge bias, and material stiffness. A fully compliant bistable micromechanism (FCBM) is used as an example, demonstrating that the approach can be used to handle complex devices involving nonlinear finite element models. The general shape of the force-displacement curve is validated by comparing the uncertainty predictions to measurements obtained from in situ force gauges. A robust design is presented, where simulations show that the estimated force variation at the point of interest may be reduced from /spl plusmn/47 /spl mu/N to /spl plusmn/3 /spl mu/N. The reduced sensitivity to process variations is experimentally validated by measuring the second stable position at multiple locations on a wafer.     

Discussion of tooling solutions for the direct bonding of silicon wafers

Silicon-to-silicon fusion (or direct) pre-bonding is an important enabling technology for many emerging microelectronics and MEMS technologies. A silicon–silicon direct bond can be easily formed, where the wafer surfaces are highly flat and very clean (Tong and Gosele), however for practical structured MEMS devices, wafer bow and local roughness may be compromised such that it is no longer a trivial task to achieve a direct bond. Tooling has been developed to facilitate the in situ alignment and bonding of silicon-to-silicon wafers in a vacuum chamber. The rate and direction of the bond propagation are controlled, thus minimising the occurrence of non-particle related voids. The tooling system also allows wafers with “non-ideal” surfaces or warped profiles to be bonded, by maximising the area across which bonding occurs and providing in situ annealing. The ability to anneal the wafers while maintaining clamping force creates attractive forces high enough to overcome the mechanical repulsive forces between the wafers and maintain a permanent bond. The tooling system can also be configured to give control over the bow or residual stress in the bonded pair, a factor that is critical in multi-stack direct wafer bonding.     

MEMS晶圆级测试系统现状及未来展望

微机电系统（ MEMS）产品的广泛应用使得晶圆级测试技术必要性日益凸显。分析了国内和国际MEMS晶圆级测试系统硬件和MEMS晶圆级测试技术的现状。参照国际上利用RM8096/8097标准物质（ RM）对MEMS产品进行计量测试的方法,给出了针对我国现有MEMS晶圆级测试系统校准问题的初步解决方案。并指出了该类测试系统今后向着标准化模块化方向发展的趋势。     

Glass frit bonding: an universal technology for wafer level encapsulation and packaging

This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass–frit bonding.     

Wafer-scale microdevice transfer/interconnect: its application in an AFM-based data-storage system

We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer, and interconnect method for batch fabricating systems on chip that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 free-standing cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver wafer (typically CMOS). Such an array is used in a highly parallel, scanning-probe-based data-storage system, which we internally call "millipede." A very high-integration density has been achieved, even for wafer-scale transfer, thanks to the interlocking nature of the interconnect structure, which provides easy alignment with an accuracy of 2 /spl mu/m. The typical integration density is 100 cantilevers/mm/sup 2/ and 300 electrical interconnects/mm/sup 2/. Note that only the cantilevers, not a chip with cantilevers, are transferred and, unlike flip-chip technology, our method preserves the device orientation, which is crucial for MEMS applications, where often the MEMS device should have access to its environment (in our case, the cantilever tips are in contact with the storage medium). After device transfer, the system is mechanically and electrically stable up to at least 500/spl deg/C, allowing post-transfer wafer processing.     

Improved process flow for buried channel fabrication in silicon

The fabrication of microchannels using MEMS technology always attracted the attention of researchers and designers of microfluidic systems. Our group focused on realizing buried fluidic channels in silicon substrates involving deep reactive ion etching. To meet the demands of today’s complex microsystems, our aim was to create passive microfluidics in the bulk Si substrate well below the surface, while retaining planarity of the wafer. Therefore additional lithographic steps for e.g. integrating circuit elements are still possible on the chip surface. In this paper, a more economic process flow is applied which also contains a selective edge-masking method in order to eliminate under-etching phenomenon at the top of the trenches to be filled. The effect of Al protection on the subsequent etch steps is also discussed. Applying the proposed protection method, our group successfully fabricated sealed microchannels with excellent surface planarity above the filled trenches. Due to the concept, the integration of the technology in hollow silicon microprobes fabrication is now available.     

Novel interconnection technology for heterogeneous integration of MEMS�CLSI multi-chip module

We developed novel interconnection technology for heterogeneous integration of MEMS and LSI multi-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked each others. The cavity chip composed of deep Cu TSV-beam lead interconnections was developed for interconnecting MEMS chips with high step height of more than few hundreds micrometer without the degradation of sensing elements. Fundamental characteristics were successfully obtained from pressure sensing MEMS chip with 360 μm thickness, which was connected to Si substrate by the cavity chip. MEMS and LSI chips were vertically integrated by using the cavity chip without any changing of chip design and extra processes. This interconnection technology can give strong solution for heterogeneous integration of MEMS and LSI chips multi-chip module.     

Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect

In this paper, we developed a hermetic wafer level packaging for MEMS devices. Au–Sn eutectic bonding technology in a relatively low temperature is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of 1 mm × 1 mm × 700 μm, and a square loop Au–Sn metallization of 70 μm in width for hermetic sealing. The robustness of the package is confirmed by several tests such as shear strength test, reliability tests, and hermeticity test. The reliability issues of Au–Sn bonding technology, and copper through-wafer interconnection are discussed, and design considerations to improve the reliability are also presented. By applying O₂ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface. The mechanical effects of copper through-vias are also investigated numerically and experimentally. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, copper diffusion phenomenon, and cleaning process. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process.     

Long-Term and Accelerated Life Testing of a Novel Single-Wafer Vacuum Encapsulation for MEMS Resonators

We have developed a single-wafer vacuum encapsulation for microelectromechanical systems (MEMS), using a thick (20-mum) polysilicon encapsulation to package micromechanical resonators in a pressure <1 Pa. The encapsulation is robust enough to withstand standard back-end processing steps, such as wafer dicing, die handling, and injection molding of plastic. We have continuously monitored the pressure of encapsulated resonators at ambient temperature for more than 10 000 h and have seen no measurable change of pressure inside the encapsulation. We have subjected packaged resonators to >600 cycles of -50 to 80degC, and no measurable change in cavity pressure was seen. We have also performed accelerated leakage tests by driving hydrogen gas in and out of the encapsulation at elevated temperature. Two results have come from these hydrogen diffusion tests. First, hydrogen diffusion rates through the encapsulation at temperatures 300-400degC have been determined. Second, the package was shown to withstand multiple temperature cycles between room and 300-400degC without showing any adverse affects. The high robustness and stability of the encapsulation can be attributed to the clean, high-temperature environment during the sealing process