Dicing challenges in microelectronics and micro electro-mechanical systems (MEMS)

 Both in semiconductor and micro electro-mechanical systems (MEMS) technology, a back end machining process is detaching the individual components by dicing the wafer into chips. To maximize the wafer surface available for integrated circuits or MEMS devices, the street width between the component structures has to be kept at a minimum. Therefore, there is a continuous thrust to minimize edge chipping as well as reduce the dicing wheel width. Furthermore, the dicing process may induce subsurface damages and microcracks particularly detrimental for packaging technology like flip chip technology, putting strain on the chip. Reducing the feed rate will result in a cutting mechanism which not only minimizes edge chip formation but also microcrack. By using gang wheels, the productivity may be maintained despite a lower feed rate.     

Die separation and packaging of a surface micromachined piezoresistive pressure sensor

The processing steps required to obtain a useful single medical sensor assembly are discussed, starting from an entire silicon wafer with thousands of surface micromachined sensors. Experiences concerning dicing and packaging of a piezoresistive pressure sensor are described, together with proposals for solutions. Problems with fracture of essential sensor structures are solved by use of a wafer protection tape. Existing solutions for flip–chip bonding and design of substrate for electrical interconnection are pushed to their limits due to the very small size of the novel sensor. As many of the processes can be simplified by an improved MEMS design, critical points related to the design are addressed.     

CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.     

Low temperature Si/Si wafer direct bonding using a plasma activated method

Manufacturing and integration of micro-electro-mechanical systems (MEMS) devices and integrated circuits (ICs) by wafer bonding often generate problems caused by thermal properties of materials. This paper presents a low temperature wafer direct bonding process assisted by O₂ plasma. Silicon wafers were treated with wet chemical cleaning and subsequently activated by O₂ plasma in the etch element of a sputtering system. Then, two wafers were brought into contact in the bonder followed by annealing in N₂ atmosphere for several hours. An infrared imaging system was used to detect bonding defects and a razor blade test was carried out to determine surface energy. The bonding yield reaches 90%–95% and the achieved surface energy is 1.76 J/m² when the bonded wafers are annealed at 350 °C in N₂ atmosphere for 2 h. Void formation was systematically observed and elimination methods were proposed. The size and density of voids greatly depend on the annealing temperature. Short O₂ plasma treatment for 60 s can alleviate void formation and enhance surface energy. A pulling test reveals that the bonding strength is more than 11.0 MPa. This low temperature wafer direct bonding process provides an efficient and reliable method for 3D integration, system on chip, and MEMS packaging.     

Novel combined through-wafer-groove fabrication approach and its application in wafer level packaging of GaAs CCD

This paper presents a novel combined through-wafer-groove fabrication approach, which is applied to the wafer level packaging (WLP) of GaAs charge coupled devices (CCD) for electrical interconnection. The combined methodology includes mechanical dicing of the groove and wet chemical etching for polishing. The parameters of the mechanical dicing are researched, including feed speed, dicing directions of the wafer, and cutting depth, to minimize the chipping. Two kinds of chemical solution are tried, and the results are discussed. Besides, the etch rate is measured, which provides a guideline for the process design. Finally, GaAs-CCD WLP sample is achieved and the electrical properties are tested to validate the feasibility of this fabrication approach. This methodology is featured by low cost, low process temperature, and good process uniformity.     

Self-aligned 0-level sealing of MEMS devices by a two layer thin film reflow process

Many micro electromechanical systems (MEMS) require a vacuum or controlled atmosphere encapsulation in order to ensure either a good performance or an acceptable lifetime of operation. Two approaches for wafer-scale zero-level packaging exist. The most popular approach is based on wafer bonding. Alternatively, encapsulation can be done by the fabrication and sealing of perforated surface micromachined membranes. In this paper, a sealing method is proposed for zero-level packaging using a thin film reflow technique. This sealing method can be done at arbitrary ambient and pressure. Also, it is self-aligned and it can be used for sealing openings directly above the MEMS device. It thus allows for a smaller die area for the sealing ring reducing in this way the device dimensions and costs.The sealing method has been demonstrated with re-flowed aluminium, germanium, and boron phosphorous silica glass. This allows for conducting as well as non-conducting sealing layers and for a variety of allowable thermal budgets. The proposed technique is therefore very versatile.The authors would like to thank Sherif Sedky for deposition of LPCVD Ge and some PECVD Ge. The authors would also like to thank to Silvia Kronmueller from Robert Bosch GmbH, Germany for fruitful discussions. This work is partly financed by the IST project SUMICAP (IST-1999–10620) of the European Commission     

Monolithically integrated photonic and optoelectronic circuits based on InP – System applications,technology, perspectives

 A severe bottleneck for the realisation of the future OTDM/WDM broadband Internet are on the component side. Under this issue the potential of Photonic ICs (PICs)/Opto-Electronic ICs (OEICs) based on InP with their photonic, opto-electronic and electronic functionalities are sketched as a central building block of planar optical/opto-electrical assemblies. Received: 27 June 2001/Accepted: 15 August 2001 The author would like to thank all people involved in the subject. This paper was presented at the Workshop “Optical MEMS and Integrated Optics” in June 2001.     

Fabrication and flow-sensor application of flexible thermal MEMS device based on Cu on polyimide substrate

A Cu on polyimide (COP) substrate was proposed as a MEMS material, and the fabrication process for a flexible thermal MEMS sensor was developed. The COP substrate application to MEMS devices has the advantage that typical MEMS structures fabricated in a SOI wafer in the past—such as a diaphragm, a beam, a heater formed on a diaphragm—can also be easily produced in the COP substrate in the flexible fashion. These structures can be used as the sensing element in various physical sensors, such as flow, acceleration, and shear stress sensors. A flexible thermal MEMS sensor was produced by using a lift-off process and sacrificial etching of a copper layer on the COP substrate. A metal film working as a flow sensing element was formed on a thin polyimide membrane produced by the sacrificial etching. The fabricated flexible thermal MEMS sensor was used as a flow sensor, and its characteristics were evaluated. The obtained sensor output versus the flow rate curve closely matched the approximate curve derived using King’s law. The rising and falling response times obtained were 0.50 and 0.67 s, respectively.

     

A mold and transfer technique for lead-free fluxless soldering and application to MEMS packaging

This paper demonstrates a technique to premold and transfer lead-free solder balls for microelectrocmechanical systems (MEMS)/electronics packaging applications. A reusable bulk micromachined silicon wafer is used to mold a solder paste and remove excess flux prior to transfer to a host wafer that may contain released MEMS. This technique has been used to fabricate low temperature thin film MEMS vacuum packages. Long term (>5 months) reliability of these packages at room temperature and pressure is demonstrated through integrated Pirani gauges. These packages have survived over 600 hours in an autoclave (130/spl deg/C, 85% RH, 2 atm) and more than 1300 temperature cycles (55/spl deg/C to 125/spl deg/C).     

Ultra thin ICs and MEMS elements: techniques for wafer thinning,stress-free separation,assembly and interconnection

 Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the “Dicing-by-Thinning” (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting. Received: 6 July 2001/Accepted: 26 February 2002 The authors would like to thank M. Küchler (IZM Chemnitz) for preparing and performing trench etching process and A. Ostmann (IZM Berlin) for performance of nickel bumping process. This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

A wireless and passive wafer cleanliness monitoring unit via electromagnetic coupling for semicondutcor/MEMS manufacturing facilities

This paper presents a wireless and passive chemical sensing system, in situ real time, via electromagnetic (EM) coupling, capable of monitoring wafer cleanliness during rinsing process at semiconductor/MEMS manufacturing facilities. A MEMS chemical sensor is embedded in a wafer-form transponder to evaluate the rinsing process in situ by measuring the conductivity of rinsing water inside micro-features formed by two interdigitated electrodes. All necessary power for the transponder is supplied from an external interrogator via the on-wafer transponder antenna. The modulated conductivity data is then emitted back from the transponder to the external interrogator in wireless and battery-free manner. The wireless system has been implemented on a 4-inch glass wafer to maintain the wafer form factor, not disturbing hydrodynamics of the rinsing process. The working distance of the system was measured to be about 25 cm, primarily limited by the coupled power to the transponder. Real time and in situ characterization of system was performed with three different control solutions: hydrochloric acid (HCl), sulfuric acid (H₂SO₄), and sodium hydroxide (NaOH). Detection uncertainty of the system was observed to be less than 2% (2 ppb for a 100 ppb solution).     

Power delivery and locomotion of untethered microactuators

The ability for a device to locomote freely on a surface requires the ability to deliver power in a way that does not restrain the device's motion. This paper presents a MEMS actuator that operates free of any physically restraining tethers. We show how a capacitive coupling can be used to deliver power to untethered MEMS devices, independently of the position and orientation of those devices. Then, we provide a simple mechanical release process for detaching these MEMS devices from the fabrication substrate once chemical processing is complete. To produce these untethered microactuators in a batch-compatible manner while leveraging existing MEMS infrastructure, we have devised a novel postprocessing sequence for a standard MEMS multiproject wafer process. Through the use of this sequence, we show how to add, post hoc , a layer of dielectric between two previously deposited polysilicon films. We have demonstrated the effectiveness of these techniques through the successful fabrication and operation of untethered scratch drive actuators. Locomotion of these actuators is controlled by frequency modulation, and the devices achieve maximum speeds of over 1.5 mm/s.     

Package hermeticity testing with thermal transient measurements

Thermal transient testing, a well known technique for thermal characterization of IC packages (Rencz and Székely 2001) can be a suitable method for detecting hermeticity failures in packaged semiconductor and MEMS devices. In the paper this measuring technique is evaluated. Experiments were done on different measurement setups at different ambient temperature and RH levels. Based on the results, a new method for package hermeticity testing is proposed.     

Characterization and failure analysis of MEMS: high resolution optical investigation of small out-of-plane movements and fast vibrations

A high resolution optical tool is required to investigate the mechanical behavior and failure modes of micro-electromechanical systems (MEMS). We report on the possibilities of a newly developed optical characterization tool for MEMS devices. Both slow movements and fast mechanical vibrations up to 15 MHz can be monitored. The instrument can perform an imaging operation for a complete image at once by employing laser TV holography, which is a large advantage over scanning laser Doppler vibrometers. For vibration measurements, this new, interference based instrument uses a beat frequency between object excitation and reference beam excitation. A normal CCD camera is used to obtain 3D images and movies of periodic mechanical motions of MEMS devices. Excitation can be by means of a PZT, or by using electronic excitation. We show that the instrument is a very useful tool for the characterization and failure analysis of MEMS devices.The whole MEMS team at IMEC and their coworkers in projects are thanked for providing many of the samples shown in this paper. In particular, we would like to thank the following people. Melexis is thanked for providing the membrane sample of Fig. 4–6 and 14. Figs. 7–9 were measured in the frame of the MISTRA project (IWT contract 000167). Theo Rijks (Philips Natlab) provided the sample of Figs. 10 and 11. Chris Muhlstein sent the sample of Fig. 12 to us. Hans de Vries (Philips Centre for Industrial Technology/EP&A) is thanked for providing the sample of Fig. 13. The switch of Fig. 15 was made in the MIRS project (5012352345). Laurent Francis (IMEC) is thanked for providing the sample of Fig. 16. Sjoerd van de Geijn of Océ-Technologies B.V. provided the sample of Fig. 17.     

MEMS晶圆级测试系统现状及未来展望

微机电系统（ MEMS）产品的广泛应用使得晶圆级测试技术必要性日益凸显。分析了国内和国际MEMS晶圆级测试系统硬件和MEMS晶圆级测试技术的现状。参照国际上利用RM8096/8097标准物质（ RM）对MEMS产品进行计量测试的方法,给出了针对我国现有MEMS晶圆级测试系统校准问题的初步解决方案。并指出了该类测试系统今后向着标准化模块化方向发展的趋势。     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

Microrivets for MEMS packaging: concept, fabrication, and strengthtesting

Microriveting is introduced as a novel and alternative joining technique to package MEMS devices. In contrast to the existing methods, mostly surface bonding, the reported technique joins two wafer pieces together by riveting, a mechanical joining means. Advantages include wafer joining at room temperature and low voltage, and relaxed requirements for surface preparation. The microrivets, which hold a cap-base wafer pair together, are formed by filling rivet holes through electroplating. The cap wafer has a recess to house the MEMS devices and also has through-holes to serve as rivet molds. The seed layer on the base wafer becomes the base of the rivet. The process requires only simple mechanical clamping of the wafer pair during riveting, compared with the more involved procedures needed for wafer bonding. Directionality of electroplating in an electric field is what makes this process simple and robust. Strength testing is carried out to evaluate the joining with microrivets. Different modes of rivet failure under different loading conditions are identified and investigated. Effective strength between 7 and 11 MPa was measured under normal loading with nickel microrivets. Joining strengths comparable to conventional wafer bonding processes, ease of fabrication with repeatability, and compatibility with batch fabrication show that microriveting is a feasible technique to join wafers for MEMS packaging, especially when hermetic sealing is not essential     

现代微电子行业的新型湿法清洗工艺

随着半导体技术的不断发展,集成电路的线宽在不断减小,对硅抛光片表面质量的要求也越来越高,为使芯片上的器件功能正常．避免硅片制造中的沾污是绝对必要的。传统的RCA清洗方法已不能满足其需求。因此,必须发展新的清洗方法。本文对传统的RCA清洗方法进行了简单的介绍,在此基础上,介绍新发展的HF／O3清洗法,从而对450mm硅片清洗方法的未来发展方向进行了简单论述。     

A new approach for handling and transferring of thin semiconductor materials

 Based on the fracture mechanics analysis of crack propagation, the phenomenon of subcritical crack growth was utilized for a controlled debonding of directly wafer-bonded interfaces. The approach allowed the well-defined separation of bonded wafers although the bond strength was high due to thermal annealing. The achieved splitting velocity depended on the wafer material, the wafer thickness ratio, the bonding process parameters, and the environmental conditions during cleaving. In combination with wafer bonding, the method can be used for a temporary stiffening and handling of thin and brittle wafers during fabrication, even if the wafers are exposed to high process temperatures. The approach can also be applied to fabricate micromechanical systems (MEMS). Received: 12 July 2001/Accepted: 26 February 2002 This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

Evaluation of Si liquid cooling structure with microchannel and TSV for 3D application

The development of 3D integration has caused a major technology paradigm shift to all integrated circuit (IC) devices, interconnects, and packages. Despite the benefits of 3D integration, this process faces the key challenge of thermal management, especially for high power and high density IC devices. Due to the limitations of conventional thermal solutions, liquid cooling technology has become a field of great interest for IC thermal management. In this study, an on-chip liquid cooling module with three different through Si vias (TSVs) and a fixed microchannel structure has been fabricated on an Si wafer using deep reactive ion etching and anodic bonding, followed by a grinding and dicing process. Pressure drop, coolant flow, and temperature difference before and after liquid flow were experimentally measured. TSV depth and diameter have been shown to have little effect on the change of pressure drop; however, shallower TSV depth and larger TSV diameter led to improved liquid cooling performance. The trapezoidal TSV showed slightly more effective cooling than did the scalloped TSV or the straight TSV.