Yield analysis for self-repairable MEMS devices

In this paper, yield analysis for a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n  +  m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. The yield model for MEMS redundancy repair is developed by statistical analysis. Based upon the yield model, the yield increase after redundancy repair for different m and n numbers is analyzed. ANSYS Monte Carlo simulation is used to estimate the yield of BISR/non-BISR MEMS devices with random point-stiction defects. The simulation results are in good agreement with the theoretical prediction based on our yield model. The simulation results also show that the SRMEMS leads to effective yield increase compared to non-BISRS design, especially for a moderate initial yield.     

Redundant-system demonstrated-reliability approximation usingpiece-part failure rates

A method of obtaining the reliability of a redundant system when only the part force-of-mortality estimates (hazard rates) for electronic parts are available is presented. Part failures are reported without specifying whether the parts are configured in series or in parallel. The sum of all the part failure rates in the system, recorded from the turn-on date of the system up to the present time of monitoring, and the sum of the failure rates of all the parts in the system recorded up to a certain previous time after the system turn-on date are calculated. The system reliability for a certain critical mission time, with or without redundancy, is calculated at that previous time. The method is useful in field-equipment reliability monitoring because exact computation is impossible without knowing whether the failed parts are configured in series or in parallel. Generally, Monte Carlo simulation should be used only to verify the results calculated through an analytic method, if such a method is available and is neither time consuming nor cost prohibitive. A dimensionless reliability parameter is introduced     

Yield optimization in large RAM's with hierarchical redundancy

The authors present and analyze large RAM architectures with hierarchical redundancy and determine the optimal redundancy organization for yield enhancement. A two-level redundancy scheme is used for defect tolerance, and the defect distribution is modeled using the compounded Poisson model. The tree random access memory (TRAM), which has been proposed as a design methodology for future multimegabit memories (N. Jarwala et al., 1988) is considered as an example for modeling and optimization. The results show that the two-level hierarchical redundancy approach, with spare bit and word lines within memory quadrants, and additional spare modules for global sparing, along with redundant interconnections can efficiently provide defect tolerance and viable yields for future generations of high-density dynamic random access memories     

A load-capacity interference model for common-mode failures in1-out-of-2: G systems

Load-capacity (stress-strength) interference theory is used to model the time-dependent behavior of a 1-out-of-2: G redundant system and to examine common-mode failures. For single units subjected to Poisson distributed load arrivals, the random failures, infant mortality, and aging are associated with load variability, capacity variability, and capacity deterioration, respectively. This paper extends the analysis to a redundant system by using a Markov model to treat Poisson distributed loads arriving at units simultaneously. Loss of s-independence of the unit failures is analyzed with joint PDFs of load and capacity. In the rare-event approximation, the degree of redundancy loss is characterized by expressing the coefficient in the beta-factor method in terms of the load and capacity distributions     

A semi-empirical model of surface scattering for Monte Carlosimulation of silicon n-MOSFETs

A semi-empirical model of surface scattering for Monte Carlo simulation of electrons in the silicon inversion layer at 300 K is proposed. The model compares favorably with different sets of experimental electron effective mobility data over a wide range of normal electric fields, channel impurity concentrations, and substrate bias. Comparisons between Monte Carlo and drift-diffusion simulations show that the model is able to correctly predict the device termination currents in the regime where nonequilibrium transport effects are negligible. It is expected therefore that at small device lengths the Monte Carlo predictions are also quantitatively correct     

Efficient simulation of digital transmission over WSSUS channels

This paper proposes an efficient Monte Carlo method which reduces computation for digital communication simulations over a multipath Rayleigh fading, wide-sense-stationary uncorrelated-scattering (WSSUS) channel. An equivalent discrete-time channel representation, which can be realized by a FIR filter with time-variant tap gains, is employed. In the proposed method, the tap gains are generated from a linear transformation of a set of orthogonal zero-mean complex Gaussian random processes. By the central limit theorem, each random process is approximated by summing a finite number of randomly generated phasors (Monte Carlo approximation). When compared with the tap gain generation method, which approximates the physical channel by the Monte Carlo approximation first and then generates the tap gain values, the proposed method demonstrates a considerable reduction in the required simulation time as well as improved accuracy under similar conditions     

Modification of Poisson statistics: modeling defects induced by diffusion

This paper examines a model of LSI device failure and the departure from Poisson statistics that it necessitates. By visually mapping anodically decorated transistors, the authors found that in highly defective sites, emitter-collector shorts-pipes-tend to collect in clusters of totally defective areas. Less defective sites have a nearly random distribution of defects, though some limited clustering may still exist. In general, a slightly curved relationship is obtained when the logarithm of actual yield is plotted versus area. However, for a small enough area, such as a single chip, one can make a linear approximation and use it to estimate the fraction of the area that is totally defective, and the defect density. The paper describes an analytical method of modeling device failures, and of projecting yields for areas larger than the data base from which the parameters of the yield equation were estimated.     

FPGA-based Monte Carlo simulation for fault tree analysis

The reliability analysis of critical systems is often performed using fault-tree analysis. Fault trees are analyzed using analytic approaches or Monte Carlo simulation. The usage of the analytic approaches is limited in few models and certain kinds of distributions. In contrast to the analytic approaches, Monte Carlo simulation can be broadly used. However, Monte Carlo simulation is time-consuming because of the intensive computations. This is because an extremely large number of simulated samples may be needed to estimate the reliability parameters at a high level of confidence.In this paper, a tree model, called Time-to-Failure tree, has been presented, which can be used to accelerate the Monte Carlo simulation of fault trees. The time-to-failure tree of a system shows the relationship between the time to failure of the system and the times to failures of its components. Static and dynamic fault trees can be easily transformed into time-to-failure trees. Each time-to-failure tree can be implemented as a pipelined digital circuit, which can be synthesized to a field programmable gate array (FPGA). In this way, Monte Carlo simulation can be significantly accelerated. The performance analysis of the method shows that the speed-up grows with the size of the fault trees. Experimental results for some benchmark fault trees show that this method can be about 471 times faster than software-based Monte Carlo simulation.     

Impact of correlated generation of oxide defects on SILC and breakdown distributions

A three-dimensional Monte Carlo model for analysis of the reliability of flash memory arrays is developed, and applied to thin tunnel oxide (t/sub ox/ = 5 nm) samples. Good agreement between experimental data and simulation results are obtained, assuming a correlated defect generation in the tunnel oxide of our samples as evidenced in (Ielmini et al., 2004). The impact of correlated defect generation on dielectric breakdown is also addressed by means of a percolation model. It is shown that correlated generation provides no significant degradation of the breakdown lifetime with respect to Poisson statistics.     

Model of multi-island single-electron arrays based on the Monte Carlo method

A two-dimensional model of multi-island single-electron arrays, based on a numerical solution to the Poisson equation and the Monte Carlo method, is suggested. The adequacy of the model is shown by com-paring the I-V characteristics calculated for two different five-island structures with experimental data. This model was used to assess quantitatively a number of geometrical parameters of a single-electron device structure, which are difficult to determine experimentally.     

Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation

This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but computationally expensive (comprehensive Monte Carlo simulation), or overly simple (fixed corner design) and unable to capture crucial statistical variation concern, dominant in sub-100-nm designs. By mathematically combining the separate Monte Carlo simulation results of SRAM cells and each peripheral block, we show that the distribution of the SA input voltage can be estimated accurately in a case where fixed corner simulation underestimates by 19%. We also present the yield equation by combining the SA input voltage and the SA offset distribution, which can be used to choose the design point. In addition, yield sensitivities are derived from the yield data to make sure that the yield has good dependence to design variables.      

Modeling manufacturing yield and reliability

In this paper, we introduce the concept of reliability defect, present the time-dependent defect growth model during operations based on a defect-related gate oxide breakdown mechanism, and build the yield-reliability relation model. Discussions presented here can also be applicable to other device failures when different physics-of-failure mechanisms are found. Through the relation model, it is possible to find a minimum level of latent defect screening to assure the required level of reliability and predict reliability for new products when it is combined with a yield prediction model     

VLSI成品率预测与仿真

本文建立ＩＣ光刻工艺相关缺陷计算模型和基于Ｍｏｎｔｅ Ｃａｒｌｏ统计成品率计算模型。阐述了集成电路功能优品率仿真系统ＸＤ－ＹＥＳ实现，讨论了应用ＸＤ－ＹＥＳ实现的功能成品率设计，并给出该系统实用性验证。研究分析表明，其结果与实际结果符合很好。     

Yield optimization of modular and redundant multimegabit RAMs: astudy of effectiveness of coding versus static redundancy using thecenter-satellite model

To determine the optimal redundancy organization for yield enhancement, redundant and modular memories are analyzed using the center-satellite model. The model suggests that the degree of redundancy for a memory module be determined according to its distance from the periphery of the wafer since the defect density increases as the periphery is neared. Analytical expressions are formulated for the yield of memory modules with extra rows and/or extra columns, coding, and coding with extra rows. Results from the analysis suggest that, for high levels of defect densities, coding can be more effective than simple extra rows and columns. For high levels of defect densities, coding with extra rows is shown to offer even better yield. For low levels of defect densities, though, just extra rows and columns may be sufficient for a high yield. An optimal amount of redundancy can be found to achieve the highest possible yield using the model that considers precise cluster distributions on the wafer, defects in a cluster, and the radial variation of these defects     

Fault-tolerant hypercube multiprocessors

The author presents a new design, called fault-tolerant hypercube (FTH), obtained by augmenting the hypercube topology with some extra links. The FTH has a graceful degradation in performance with the existence of faults. The hardware (link redundancy) is small and negligible for hypercubes with large dimensions. A probabilistic model based on a Markov chain characterizes the FTH-subcube reliability. The mean time to failure is at least 22% better than that for the conventional hypercube. The results have been verified by Monte Carlo simulation. The FTH design is simple and easy to implement. This network can lend itself to the execution of many parallel algorithms designed to run on hypercubes. The FTH contains many more subcubes than the standard hypercube, and thus executes tasks requiring various cube sizes. Where allocation and deallocation of tasks to various subcubes is a common practice, this design achieves an excellent processor usage by efficiently and compactly assigning subcubes     

Fast and accurate statistical characterization of standard cell libraries

With devices entering the nanometer scale process-induced variations, intrinsic variations and reliability issues impose new challenges for the electronic design automation industry. Design automation tools must keep the pace of technology and keep predicting accurately and efficiently the high-level design metrics such as delay and power. Although it is the most time consuming, Monte Carlo is still the simplest and most employed technique for simulating the impact of process variability at circuit level. This work addresses the problem of efficient alternatives for Monte Carlo for modeling circuit characteristics under statistical variability. This work employs the error propagation technique and Response Surface Methodology for substituting Monte Carlo simulations for library characterization.The techniques are validated and compared using a production level cell library using a state-of-the-art 32 nm technology node and statistical device compact model. They require electrical simulation effort linear to the number of devices, thus from one to two orders of magnitude speed-up is obtained compared to Monte Carlo analysis with the error on standard deviation and mean being smaller than 2% for the Response Surface Methodology, as compared to errors of 7% when using linear sensitivity analysis.     

An Age-Based Inspection and Replacement Policy for Heterogeneous Components

This paper considers a hybrid maintenance policy for a single component from a heterogeneous population. The component is placed in a socket, and the component and socket together comprise the system. The $s$-population of components consists of two sub-populations with different failure characteristics. By supposing that a component may be in a defective but operating state, so that there exists a delay time between defect arrival and component failure, we consider a novel maintenance policy that is a hybrid of inspection and replacement policies. There are similarities in this approach with the concept of “burn-in” maintenance. The policies are investigated in the context of traction motor bearing failures. Under certain circumstances, particularly when the mixture parameter is large, and the distribution of lifetimes for the two component types are well separated, the hybrid policy has significant cost savings over the standard age-based replacement policy, and over the pure inspection policy. In addition to the cost metric, the mean time between operational failures of the system under the hybrid policy can be used to guide decision-making. This maintenance policy metric is calculated using simulation, and using an approximation which assumes that operational failures occur according to a Poisson process with a rate that can be calculated in a straightforward way. The simulation results show good agreement with the approximation.      

An Empirical Bayes Approach for the Poisson Life Distribution

A smooth empirical Bayes estimator is derived for the intensity parameter (hazard rate) in the Poisson distribution as used in life testing. The reliability function is also estimated either by using the empirical Bayes estimate of the parameter, or by obtaining the expectation of the reliability function. The behavior of the empirical Bayes procedure is studied through Monte Carlo simulation in which estimates of mean-squared errors of the empirical Bayes estimators are compared with those of conventional estimators such as minimum variance unbiased or maximum likelihood. Results indicate a significant reduction in mean-squared error of the empirical Bayes estimators over the conventional variety.     

Numerical analysis of nonequilibrium electron transport inAlGaAs/InGaAs/GaAs pseudomorphic MODFETs

Nonequilibrium electron transport in InGaAs pseudomorphic MODFETs has been analyzed with the moment equations approach. In the model, the momentum and energy balance equations for the two-dimensional electrons in the InGaAs channel are solved with relaxation times generated from a Monte Carlo simulation. The two-dimensional electron wave functions and the quantized state energies in the InGaAs quantum well are calculated exactly from the Schrodinger equation along the direction perpendicular to the quantum well. Also included is a two-dimensional Poisson equation solver. In the calculation, all of the equations are solved iteratively until a self-consistent solution is achieved. The simulation results for a realistic device structure with a 0.5-μm recessed gate show a significant overshoot velocity of 4.5×10⁷ cm/s at a drain bias of 1.0 V. Electron temperature reaches a peak value of around 2500 K under the gate. In energy transport, the diffusive component of the energy flux is found to be dominant in the high-field region     

Ergodic capacity formula of MIMO-OFDM systems under correlated frequency selective Rayleigh fading channels

An explicit formula for the ergodic capacity of Orthogonal Frequency Division Multiplexing (OFDM)-based Multiple-Input Multiple-Output (MIMO) systems under correlated frequency selective Rayleigh channels is derived,by simplifying the channel response matrix in frequency domain into the so-called Kronecker model composed of three kinds of correlations,i.e.multipath tap gain correlation and spatial fading correlations at both transmitter and receiver.The derived formula is very simple and convenient for one to estimate the effects of all three kinds of correlations on MIMO-OFDM capacity.If taps are independent,there is a very simple expression for the ergodic capacity.In case of tap correlation,the capacity formula could be further given in an integral expression.The validity of the new formula is verified and the effects of correlations,delay spread as well as the number of subcarriers on the ergodic capacity are evaluated via Monte Carlo simulations.