Bias temperature reliability of p-channel high-voltage devices

Important shifts in the threshold voltage of high voltage p-channel DMOS transistors have been observed. These shifts are strongly dependent on the stress conditions.An empirical degradation model is derived from measurement data. For a given allowed shift in threshold voltage, this model can determine the safe operating area of the device.The shift in threshold voltage in the p-channel DMOS transistors is explained by excitation and trapping of holes at the oxide-silicon interface at the drain side.     

A mixed CMOS-DMOS-JFET technology for switching circuits with high voltage output stages

This paper describes the development of a technology that incorporates low voltage CMOS and high voltage JFET and DMOS transistors on the same chip. The fabrication sequence is based on a metal gate CMOS process. The influence of the process variables and trade-offs in the characteristics of the devices have been discussed. The successful application of the technology to a thermal printer head driver circuit has been demonstrated.     

Tradeoff between threshold voltage and breakdown in high-voltage double-diffused MOS transistors

The design of junction isolated DMOS transistors suitable for monolithic integration has been studied. The purpose of this correspondence is to describe one of the key tradeoffs when designing these devices for high breakdown voltages (200 V for our example). It is a tradeoff primarily between threshold voltage and the punchthrough voltage of the channel diffusion, however, the avalanche breakdown voltage, on-resistance, and source-to-substrate punchthrough voltage are also affected. As an example, the design of a device for 200-V operation is described. The discussion is, however, general and can be applied to other DMOS designs as well.     

Model for DMOST threshold voltage

An analytical model for the channel region in MOS-gated power transistors has been developed. The model takes into account the effect of substrate doping gradient on the threshold voltage of the transistor and it can be applied to lateral and vertical DMOS and IGBT transistor structures. The model has been tested by comparing the calculated I-V characteristics for an MOS structure having various doping gradients to the results from a 2-D device simulator.<>     

A high voltage UMOS transistor

A throretical and experimental study of a novel UMOS (U for U-shaped notch) transistor structure is presented. This short channel device combines a simple U-groove geometry with features similar to those of DMOS transistors. Voltage and switching capabilities are investigated. Necessary trade-offs are emphasized in the design process and the critical fabrication steps are discussed.Both the theoretical considerations as well as the experimental results indicate that the UMOS transistor described is suitable for high voltage switching applications.     

A 30 A 30 V DMOS motor controller and driver

A power DMOS half bridge (R_on=40 mΩ, 30-V operating voltage, 30 A peak current) for windshield-wiper motors is presented. Double speed (DC and 20 kHz PWM output), motor braking, full protection and fault detection functions, and timing sequence (up to 200 ms) are performed by an integrated circuit that integrates the pull-up power transistor as well as the signal circuits on a technology process that allows the integration of bipolar, CMOS, and power DMOS transistors. The power pull-down transistor is a discrete device mounted in the same power package (Multi-watt 11) on an isolated tab     

Low-Frequency Noise Partition of Asymmetric MOS Transistors Operating in Linear Regime

The low-frequency noise in asymmetric MOS transistors with graded channel doping from the source to the drain can be partitioned by assuming a series connection of two or more transistors along the device's channel length. The partition explains the noise overshoot at gate biases around the threshold voltage of the composite device. Expressions for the input-referred gate noise voltage are obtained and verified.      

A new VLSI memory cell using DMOS technology (DMOS cell)

A high-density dynamic memory cell using DMOS technology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing. Since n-DMOSFET threshold state is nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, which is made small by using two polysilicon layers and self-aligned structure, is about 50 percent of the conventional one-transistor memory cell area. An analytic model for DMOS cell readout voltage is proposed. From this model, the optimum DMOS cell structure, which gives more than 0.7-V readout voltage with 2-µm channel length, is found for 5-V power supply operation. Experimental data support this model. A 7-µA readout current per 1-µm channel width is obtained for 400-Å gate oxide test cell. The complete memory operation is confirmed with a 2 × 2 test cell array.     

A monolithic quad line driver for industrial applications

The device described in this paper is a new quad line driver to be used in the hostile and noisy industrial environment and developed in mixed technology (BCD: Bipolar, CMOS, DMOS). It consists of four independent line drivers, each of which has a rail-to-rail push-pull output stage realized with power DMOS transistors connected in half bridge configuration. Even though the device is designed to be used primarily in the output cards of programmable controllers, it is a general purpose device, since it can drive any kind of load (resistive, capacitive, or inductive) with an output current of 100 mA. The novel structure of the top driver allows full protection of the output stage against any kind of short circuits and/or overloads, providing a linear current limitation. Furthermore, when a channel is tristated, for every applied voltage ranging from ground to the supply voltage, virtually zero current is absorbed from the output. An innovative high efficiency central charge pump circuit has also been designed and implemented, making both a very wide supply voltage operation (6-50 V) and high switching frequency (up to 500 KHz) possible, The device can also be used as a receiver since the input voltage can swing from -10-50 V     

Optimum load device for DMOS integrated circuits

Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation, <1,1,1> crystal orientation should be used. The <1,1,1> crystal orientation also yields a higher transconductance for the DMOS transistor than the <1,0,0> orientation. The geometry of the load device and the DMOS transistor can be made ratioless to conserve area. Self-aligned gates, hitherto considered incompatible with DMOS transistors, have been incorporated in the structure. The experimental DMOS invertors, using a conservative design, have achieved 4-ns propagation delay, 1.3-V operation and 2-pJ propagation delay-power dissipation product.     

Silicon-on-insulator approach for power IC's integrating verticalDMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions     

Counterdoping of MOS channel (CDC)-a new technique of improvingsuppression of latching in insulated gate bipolar transistors

A novel technique of improving suppression of latching in insulated-gate bipolar transistors (IGBTs) is proposed and experimentally verified. By counterdoping the channel of the DMOS cell, the doping of the p-base can be increased up to a factor of two. Dynamic latching improvement of 40-80%, corresponding to the p-base doping increase, has been obtained. The degradation in forward blocking voltage was observed when the counterdoping dosage exceeds about 2×10¹² cm^-2 for 600-V devices     

短沟DMOS阈值电压模型

该文提出了短沟DMOS阈值电压模型。基于沟道区耗尽电荷的二维分布,计算沟道区中耗尽电荷总量,由此给出短沟DMOS阈值电压模型的计算式。该模型的解析解与二维仿真器MEDICI的数值解吻合。分析表明,DMOS沟道长度小于0.80m,就应考虑短沟效应。     

Determining the drain doping in DMOS transistors using the hump inthe leakage current

The hump in the leakage current of double-diffused metal-oxide-semiconductor (DMOS) transistors observed for low drain voltages is explained. This hump is due to surface generation current of the gate-controlled diode formed by the base-drain p-n junction. The drain bias of the DMOS transistor is shown to have the same effect on the charge at the drain surface as the body bias in the conventional MOSFET. The body effect is used to develop a new method for determining the drain doping in DMOS transistors. This method is nondestructive, and does not require special test structures. Instead, electrical measurements are performed on conventional DMOS transistors. The method is ideally suited for determining the doping in the drain region of interest. Specifically, in DMOS transistors in which a surface implant is used to reduce the on-resistance, the method provides the doping concentration in the implanted region. In DMOS transistors which do not have the surface implant, the method yields the doping concentration in the drain epitaxial layer. In this study, the method is illustrated by determining the drain doping for six discrete power MOSFET device types from three different manufacturers     

Analysis of temperature dependence of CMOS transistors' threshold voltage

In this paper an investigation of influence of the metal-semiconductor work function difference on the threshold voltage of high-temperature (up to 473 K) operating CMOS transistors, which is often neglected in the literature, is presented. Expressions for temperature dependence of the threshold voltage of both Al-gate and Si-gate CMOS transistors, which take into account the influence of the metal-semiconductor work function difference, are derived starting from the standard expression for the MOS transistor threshold voltage. The temperature coefficient of the threshold voltage is considered in more detail, to provide a simple approximate model for the temperature dependence of the threshold voltage. It is shown that neglecting the temperature dependence of the metal-semiconductor work function difference significantly affects accuracy in prediction of the threshold voltage temperature behavior.     

Radiation damage in proton-irradiated strained Si n-MOSFETs

Strained Si layers (sSi) on strain-relaxed SiGe buffer layers are frequently used in order to boost up the carrier mobility. This study investigates the degradation of such sSi n-MOSFETs by 20-MeV proton irradiation. The drain current decreases and a negative shift of the threshold voltage is observed after proton irradiation. The impact of the fabrication process of sSi transistors on the degradation is also discussed.     

Short channel erase in n-channel Si-gate MNOS EEPROM transistors

A unipolar method of erasing MNOS EEPROM transistors with short channel lengths by reverse-biasing of source and drain with gate and substrate grounded is described for n-channel Si-gate transistors. With pulse conditions kept constant, the threshold voltage shift caused by short channel erase (SCE) depends strongly on channel length and nitride thickness of the transistors. At effective channel lengths < 0.4 μm, SCE voltages V_SCE < 20 V are sufficient to cause a shift in the threshold voltage comparable to the value obtained with 25 V pulses using the conventional erase method and both voltage polarities.SCE voltage measurements at varied temperatures show that the results are in agreement with the model conception of the avalanche punch-through erase (APTE) mode. The retention data have been found regardless of the SCE treatment. Endurance has been investigated by multiple cycling of MNOS transistors using up to 10⁷ pulses of 25 V, 100 μs. The effective window width did not change, but the transconductance was found to decrease slightly with cycle number.     

Measurement and modeling of a new width dependence of nmosfet degradation

NMOS transistors with widths between 1.2μm and 10μm and length of 0.8μm have been stressed for up to 5000 hours. Investigating the threshold voltage shift a new width dependence of degradation has been measured, analysed and modeled by a simple theory. Because of the increasing degradation of NMOSFETs with decreasing width this effect will be more and more important for small-channel LOCOS transistors.     

Field-effect transistor based on ZnO nanorods with a variable threshold cutoff voltage

This study is concerned with the fabrication and electrical characteristics of short-channel (2 μm) field-effect transistors (FETs) based on ZnO nanorods. In FET fabrication, single-crystal ZnO nanorods are grown using the catalyst-free chemical vapor deposition (CVD) method. Although the short-channel ZnO-nanorod FETs exhibit good electrical characteristics (a transconductance of 100 nS, electron mobility of 6 cm² V^?1 s^?1, and a large turn-ON/OFF ratio of 10⁴), their characteristics significantly depend on the length of the nanorods. The effect of the drain-source voltage on the threshold gate voltage is studied.     

Comparison of radio frequency physical vapor deposition target material used for LaOx cap layer deposition in 32 nm NMOSFETs

The MOSFET gate length reduction down to 32 nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500 mV. Because this layer plays a key role in the device performance and strongly depends on its deposition process, we have compared two LaO_x deposition methods in terms of physical properties and influence on electrical NMOS device parameters. Chemical characterizations have shown a different oxidization state according to Lanthanum thickness deposited. It has been related to threshold voltage shift and gate leakage current variations on NMOS transistors. Furthermore mobility extractions have shown that Lanthanum is a cause of mobility degradation.