Nitrogen Plasma Processing of SiO2/4H-SiC Interfaces

A nitrogen plasma annealing process for gate dielectric applications in 4H-SiC metal oxide semiconductor (MOS) technology has been investigated. This process results in substantially greater interfacial N coverage at the SiO₂/4H-SiC interface and lower interface trap densities than the state-of-the-art nitric oxide (NO) annealing process. Despite these exciting results, the field-effect mobility of MOS field-effect transistors (MOSFETs) fabricated by use of this process is very similar to that of NO-annealed MOSFETs. These results emphasize the importance of understanding mobility-limiting mechanisms in addition to charge trapping in next-generation 4H-SiC MOSFETs.     

Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.     

Extraction of SiO2/SiC interface trap profile in 4H- and 6H-SiC metal-oxide semiconductor field-effect transistors from subthreshold characteristics at 25°C and 150°C

The profile of trap density at the SiO₂/SiC interface in SiC metal-oxide semiconductor field-effect transistors (MOSFETs) is critical to study the channel electron mobility and evaluate device performance under various processing and annealing conditions. In this work, we report on our results in determining the interface trap density in 4H- and 6H-SiC MOSFETs annealed in dry O₂, NO, and CO₂, respectively, based on the device transfer and currentvoltage characteristics in the subthreshold region at 25°C and 150°C. We also studied electron field-effect mobility, fixed oxide charge, and gate leakage in those devices.     

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Carrier traps in 4H-SiC metal–oxide–semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS field-effect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55 K. An additional peak near 80 K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N _t,hole = 2.08 × 10¹⁵ cm⁻³ at 2 MV/cm gate field and N _t,hole = 2.5 × 10¹⁶ cm⁻³ at 4.5 MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n ⁺–p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n ⁺ SiC substrate.     

Effect of process variations and ambient temperature on electron mobility at the SiO/sub 2//4H-SiC interface

We report the effect of processing variables on the inversion layer electron mobility of (0001)-oriented 4H-SiC n-channel MOSFETs. The process variables investigated include: i) implant anneal temperature and ambient; ii) oxidation procedure; iii) postoxidation annealing in nitric oxide (NO); iv) type of gate material, and v) high-temperature ohmic contact anneal. Electron mobility is significantly increased by a postoxidation anneal in NO, but other process variations investigated have only minor effects on the channel mobility. We also report the temperature dependence of electron mobility for NO and non-NO annealed n-channel MOSFETs.     

Excellent effects of hydrogen postoxidation annealing on inversionchannel mobility of 4H-SiC MOSFET fabricated on (112¯0) face

Effects of hydrogen postoxidation annealing (H₂ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112¯0) face have been investigated. As a result, an inversion channel mobility of 110 cm²/Vs was successfully achieved using H₂ POA at 800°C for 30 min. H₂ POA reduces the interface trap density by about one order of magnitude compared with that without H₂ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H₂ POA. In addition, 4H-SiC MOSFET with H₂ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm²/Vs     

Improvement of interface quality by post-annealing on silicon nanowire MOSFET devices with multi-wire channels

We have investigated the passivation effects of high-pressure hydrogen annealing (HPHA) on silicon nanowire (Si NW) metal oxide semiconductor field effect transistors (MOSFETs) with multi-wire channels. Compared to the conventional forming gas annealing (FGA) process, the results show that HPHA can significantly improve device performance parameters such as threshold voltage, subthreshold slope, mobility, and I_ON/I_OFF ratio. This enhancement is attributed to the effective passivation of the interface traps between the SiO₂ and the Si NW channel. Therefore, HPHA can be a promising process for the implementation of the Si NW MOSFET.     

SiC MOS器件界面钝化研究进展

从氧化后退火处理、氮化处理、碳帽、钡夹层、淀积氧化物后退火处理五个方面介绍了碳化硅钝化工艺。通过改进钝化工艺可以有效降低界面态密度。针对这几种钝化工艺对SiC/SiO₂界面态密度的影响进行讨论,分析几种钝化工艺的优劣,并重点介绍了氧化后退火处理和氮化处理两种钝化方法。研究发现,NO氮化工艺能有效降低界面态密度,提高界面可靠性。该工艺适用于SiC MOS器件的制造。     

Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

Phosphorous passivation of the SiO2/4H–SiC interface

We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO₂/4H–SiC interface. Annealing in a P₂O₅ ambient converts the SiO₂ layer to PSG (phosphosilicate glass) which is known to be a polar material. Higher mobility (approximately twice the value of 30–40 cm²/V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density. Trap density, current–voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed. The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O–S interface. Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel. The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly.     

Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO₂/SiC interface than NO annealing time.     

Improved oxidation procedures for reduced SiO2/SiC defects

A significant reduction in the effective oxide charge and interface state densities in oxides grown on p-type 6H-SiC has been obtained by lowering the oxidation temperature of SiC to 1050°C. Further improvements are obtained by following the oxidation with an even lower temperature re-oxidation anneal. This anneal dramatically improves the electrical properties of the Si/SiC interface, and substantially lowers the interface state density. The net oxide charge density on p-type 6H-SiC is also lowered significantly, but remains quite high, at 1.0 × 10¹² cm^-2. The interface state densities of 1.0 × 10¹¹ cnr⁻²/eV are approaching acceptable MOS device levels. The breakdown fields of the oxides are also substantially improved by both the lower oxidation temperature and re-oxidation anneal. Using a low temperature oxidation followed by a re-oxidation anneal for MOSFETs results in a room temperature mobility of 72 cm²/V-s, the highest channel mobility reported for SiC MOSFETs to date.     

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO₂/HfO₂ dielectrics (effective oxide thickness is less than 1 nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.     

Some Critical Materials and Processing Issues in SiC Power Devices

There has been a rapid improvement in SiC materials and power devices during the last few years. However, the materials community has overlooked some critical issues, which may threaten the emergence of SiC power devices in the coming years. Some of these pressing materials and processing issues will be presented in this paper. The first issue deals with the possibility of process-induced bulk traps in SiC immediately under the SiC/SiO₂ interface, which may be involved in the reduction of effective inversion layer electron mobility in SiC metal–oxide–semiconductor field-effect transistor (MOSFETs). The second issue addresses the effect of recombination-induced stacking faults (SFs) in majority carrier devices such as MOSFETs, Schottky diodes, and junction field-effect transistors (JFETs). In the past it was assumed that the SFs only affect the bipolar devices such as PiN diodes and thyristors. However, most majority carrier devices have built-in p–n junction diodes, which can become forward biased during operation in a circuit. Thus, all high-voltage SiC devices are susceptible to this phenomenon.     

Channel-carrier mobility parameters for 4H SiC MOSFETs

In this paper, mobility parameters for enhancement-mode N-channel 4H SiC MOSFETs are extracted and implemented into 2-D device simulation program and SPICE circuit simulator. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide–semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (D_it) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to a good agreement with the experimental transfer characteristic.     

Ultra-Thin Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si_1−x Ge _x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si_1−x Ge _x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si_1−x Ge _x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.     

High channel mobility in inversion layers of 4H-SiC MOSFETs byutilizing (112¯0) face

A dramatic improvement of inversion channel mobility in 4H-SiC MOSFETs was successfully achieved by utilizing the (112¯0) face: 17 times higher (95.9 cm²/Vs) than that on the conventional (0001) Si-face (5.59 cm²/Vs). A low threshold voltage of MOSFETs on the (112¯0) face indicates that the (112¯0) MOS interface has fewer negative charges than the (0001) MOS interface. Small anisotropy of channel mobility in 4H-SiC MOSFETs (μ_(11¯00)/μ₍₀₀₀₁₎=0.85) reflects the small anisotropy in bulk electron mobility     

Improved inversion channel mobility for 4H-SiC MOSFETs followinghigh temperature anneals in nitric oxide

Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO₂ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2×10¹³ to 2×10¹² eV^-1 cm^-2 following anneals in nitric oxide at 1175°C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm²/V-s following the passivation anneals     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

碳化硅MOSFET反型沟道迁移率的研究

SiC MOSFET是制作高速、低功耗开关功率器件的理想材料，然而，制作反型沟道迁移率较高的SiC MOSFET工艺尚未取得满意结果。通过在N0中高温退火可以显著地提高4H—SiC MOSFET的有效沟道迁移率；采用H2中退火制作的4H—SiC MOSFET阈值电压为3．1V，反型沟道迁移率高于100cm^2／Vs的栅压的安全工作区较宽。N20退火技术由于其的安全性而发展迅速并将取代N0。