用于CMOS图像传感器的列并行RSD循环ADC

设计了一种用于CMOS图像传感器的列并行RSD循环ADC.转换和采样同步进行,速度比传统的循环ADC提高了1倍,适用于高速实时系统的应用.将采样保持,精确乘2和像素信号的FPN噪声消除功能用1个运放和6个电容来实现,大大缩小了面积.采用RSD算法,不但降低了对比较器的精度要求,并且实现了较高的线性度.通过失调反向存储,基本消除运放失调引入的列FPN噪声.该ADC在0.18μm工艺下,实现了10位精度和500 KS/S的高转换速度.ADC的DNL= 0.5/-0.5 LsB,INL= 0.1/-1.5 LSB.     

一种应用于CMOS图像传感器的片上内插式ADC设计

设计了一种用于1024×1024CMOS图像传感器的内插式模数转换器（ADC）结构。转换采用并行处理方式,采用内插式结构,与流水线ADC相比速度更快。电路采用失调纠正技术和衬底驱动技术设计了1个低失调电压的前置全差分两级跨导运算放大器（OTA）,PMOS管作为电阻产生与锁存阈值电压相交的基准电压,具有较高的精度。基于0．35μmCMOS工艺的仿真结果表明,该ADC的DNL=0．45LSB,INL=0．65LSB,可以满足CMOS图像传感器芯片级ADC的高速高精度要求。     

一种用于时延积分CMOS图像传感器的10 bit全差分双斜坡模数转换器

为了满足时间延时积分(TDI)CMOS图像传感器转换全差分信号的需要,同时符合列并行电路列宽的限制,该文提出并实现了一种10 bit全差分双斜坡模数转换器(ADC)。在列并行单斜坡ADC的基础上,采用2个电容的上极板对差分输入进行采样,电容下极板接2个斜坡输出完成量化。基于电流舵结构的斜坡发生器同时产生上升和下降斜坡,2个斜坡的台阶电压大小相等。该电路使用SMIC 0.18 μm CMOS工艺设计实现,ADC以19.49 kS/s的采样频率对1.32 kHz的输入进行采样,仿真得到无杂散动态范围和有效位数分别为87.92 dB和9.84 bit。测试显示该ADC的微分非线性误差和积分非线性误差分别为–0.7/+0.6 LSB和–2.6/+2.1 LSB。     

用于高速CIS的12-bit紧凑型多列共享并行pipeline-SAR ADC

设计了一款用于高速CMOS图像传感器的多列共享列并行流水线逐次逼近模数转换器。八列像素共享一路pipeline-SAR ADC,从而使得ADC的版图不再局限于二列像素的宽度,可以在16列像素宽度内实现。该模数转换器采用了异步控制逻辑电路来提高转换速度。半增益数模混合单元电路被用于对第一级子ADC的余差信号放大,同时被用于降低对增益数模混合单元电路中运放性能的要求。相关电平位移技术也被用于对余差信号进行更精确的放大。整个pipeline-SAR ADC第一级子ADC精度为6-bit,第二级子ADC为7-bit,两级之间存在1-bit冗余校准,最终实现12-bit精度。输入信号满幅电压为1 V。该8列共享并行处理的pipeline-SAR ADC在0.18 m 1P4M工艺下制造实现,芯片面积为0.204 mm2。仿真结果显示,在采样频率为8.33 Msps,输入信号频率为229.7 kHz时,该ADC的信噪失真比为72.6 dB;在采样频率为8.33 Msps,输入信号频率为4.16 MHz时,该ADC的信噪失真比为71.7 dB。该pipeline-SAR ADC的电源电压为1.8 V,功耗为4.95 mW,功耗品质因子（FoM）为172.5 fJ/conversion-step。由于像素尺寸只有7.5 m,工艺只有四层金属,因此这款12-bit多列共享列并行流水线逐次逼近模数转换器非常适用于高速CMOS图像传感器系统。     

CCD图像采集系统的低功耗流水线ADC设计

设计了一个适用于面阵OCD图像采集系统的10位、90MSPS流水线ADC.通过采用低功耗动态比较器和省略输入级采样保持模块使得该高速ADC具有低功耗的优点.电路设计使用Charter 0.35μm3.3V 2P4M CMOS工艺.仿真结果表明:90MHz的采样速率、3.3MHz正弦信号输入下,该ADC模块具有9.3bit的有效分辨率,最大DNL为0.5LSB,最大INL为0.8LSB,整个ADC功耗仅为35.4mW.     

用于CMOS图像传感器的12位低功耗单斜坡模数转换器设计

 本文提出了一种应用于CMOS图像传感器中的高精度低功耗单斜坡模数转换器(single slope analog-to-digital converter)设计方案.该ADC方案由可变增益放大器、前置预放大器和动态锁存比较器组成.相比现有的设计方案,本文提出的电路在不牺牲噪声性能的前提下,具有更低的功耗和更小的芯片面积.通过集成列并行的单斜坡模数转换器在最新设计的高精度高速CMOS图像传感器设计中,实验结果证明了设计的有效性.     

基于SAR-SS架构的图像传感器专用高速列级ADC设计

针对图像传感器中传统列级模数转换器(ADC)难以实现高帧频的问题,提出了一种由逐次逼近寄存器型(SAR)ADC和单斜坡型(SS)ADC组成的混合型高速列级ADC,使转换周期相较于传统的SS ADC缩短约97%;利用SAR ADC的电容实现像素的相关双采样(CDS),在模拟域做差,使CDS的量化时间缩短至一个转换周期,进一步提高了ADC的量化速度;为了保证列级ADC的线性度,提出了一种1bit冗余算法,可实现+0.13/-0.12 LSB的微分非线性和+0.18/-0.93 LSB的积分非线性。基于180nm CMOS工艺的仿真结果表明,该列级ADC在50MHz时钟下,转换周期仅为1μs,无杂散动态范围为73.50dB,信噪失真比为66.65dB,有效位数为10.78bit。     

一种用于CMOS图像传感器的Column-Level模数转换器

设计了一种用于CMOS图像传感器(CIS)的column-level模数转换器(ADC)。它由一种新型斜坡发生器构成,具有分辨率可调的特点,而且以简单的结构实现了高精度和低功耗,占用较小的版图面积。基于0.35μm2P4M标准CMOS工艺,8bit ADC转换时间约50μs,最大线性误差小于±0.5LSB。在分辨率为640×480pixel的CIS中,每列共用1个比较器,提高了传感器的吞吐速率,帧频约40fps;3.3V电压下ADC总功耗不超过27mW,占用版图面积约0.5mm2。     

用于低噪声CMOS图像传感器的流水线ADC设计及其成像验证

在对低噪声CMOS图像传感器的研究中,除需关注其噪声外,目前数字化也是它的一个重要的研究和设计方向,设计了一种可用于低噪声CMOS图像传感器的12 bit,10 Msps的流水线型ADC,并基于0.5μm标准CMOS工艺进行了流片。最后,通过在PCB测试版上用本文设计的ADC实现了模拟输出的低噪声CMOS图像传感器的模数转换,并基于自主开发的成像测试系统进行了成像验证,结果表明,成像画面清晰,该ADC可作为低噪声CMOS图像传感器的芯片级模数转换器应用。     

小面积、微功耗增量型Sigma-Delta ADC设计

模拟数字转换器(ADC)是智能化传感器的一个重要组成部分。阵列型传感器应用对ADC的功耗及芯片面积都具有较高的要求,同时传感器本身特性要求ADC具有较高的精度,对阵列型传感器用ADC的设计提出了挑战。在分析各类型ADC的性能优劣势的基础上,提出了应用增量型Sigma-Delta ADC来设计阵列型传感器应用。介绍了增量型Sigma-Delta ADC的架构设计以及电路设计,并在0.18?m CMOS工艺下流片。在40 k S/s的转换速度下,所设计的ADC达到了15 bit的精度,功耗为58?W,单个ADC的芯片面积为10?m×530?m。测试结果表明增量型Sigma-Delta ADC非常适合于阵列型传感器应用。     

A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs

A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented. The simplified single-ended circuits for the cyclic ADC are squeezed into a 5.6-mum-pitch single-side column. The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB. An ultralow vertical fixed pattern noise of 0.1 e_rms ^- is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mus). The implemented CIS with 0.18-mum technology operates at 390 frames/s and has 7.07-V/lx middots sensitivity, 61- muV/e^- conversion gain, 4.9-e_rms ^- read noise, and less than 0.4 LSB differential nonlinearity.     

A Nyquist-rate pixel-level ADC for CMOS image sensors

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320×256 sensor using the MCBS ADC is described. The chip measures 4.14×5.16 mm². It achieves 10×10 μm² pixel size at 28% fill factor in 0.35 μm CMOS technology. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively     

An On-Sensor Bit-Serial Column-Parallel Processing Architecture for High-Speed Discrete Fourier Transform

This brief presents a discrete Fourier transform (DFT) processor based on a bit-serial column-parallel processing architecture suitable for integrating it on CMOS image sensors. Using a column-parallel A/D converter (ADC) array, column-line sensor outputs of the two-dimensional image array are digitized. The ADC outputs are sliced to one bit and are given to the bit-serial column-parallel DFT processor from the MSB to the LSB. A high-speed and cost-effective implementation can be expected. In the case of 256$,times,$256-point DFT for 8-b image data, the processing time is estimated to be 2 ms at a clock frequency of 100 MHz, which corresponds to the 500-frames/s real-time processing.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

Reduced comparator high speed low power ADC using 90 nm CMOS technology

The increasing demand of high speed and low power ADC in serial links, gigabit ethernet, high speed instruments in general and communication technologies such as ultra wide band systems in particular has put tremendous pressure on efficient design of data converters. Presently flash ADC is the architecture of choice with sampling frequency ranging from 2 to 40 GS/s with 4–6 bit resolution, where speed and low resolution is required. However we are forced to compromise between performance and complexity when such ADC is used. In this paper a single channel high speed low power CMOS based 4-bit ADC using reduced comparator and multiplexer based architecture is presented. For improving the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the proposed ADC are fully modified and the architecture uses only 4 comparators instead of 15 as used in conventional flash ADC, thereby saving considerable amount of power. The proposed 4-bit 2 GS/s ADC is designed and simulated in Tanner tools with 1.2 V supply voltage using 90 nm CMOS technology. HSpice simulation result of proposed architecture shows a power dissipation of 23 mW with INL and DNL errors between ±0.4 LSB and ±0.34 LSB respectively. ENOB and SNDR for the proposed architecture are 3.72 and 24.2 respectively.     

A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs

This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 $times$ 240 pixels has been fabricated with a 0.35- $muhbox{m}$ CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 $muhbox{s}$ , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of $+hbox{0.53}/-!hbox{0.78}$ LSB and INL of $+hbox{1.42}/-!hbox{1.61}$ LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.