A remotely-powered, 20 Mb/s, 5.35 pJ/bit impulse-UWB WSN tag for cm-accurate-localization sensor networks

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in \(0.13 \,\upmu \hbox {m}\) CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only \(113\, \upmu \hbox {W}\) during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved.     

Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS

A novel mm-wave phase modulating transmit architecture, capable of achieving data rates as high as 10 Gb/s is presented at 120 GHz. The circuit operates at a frequency of 120 GHz. The modulator consists of a differential branchline coupler and a high speed 4-to-1 analog multiplexer with direct digital input. Both a QPSK as well as a 8QAM constellation are supported. To achieve high output power, a 9-stage power amplifier is designed and connected to the multiplexer output. The complete chip is integrated in a 65 nm low power CMOS technology. Capacitive neutralization is used to achieve high gain and good stability for the MOS devices. Also, various differential transmission line topologies are investigated to achieve high performance in terms of loss and area consumption.     

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two common-source stages with a 1.5 kΩ feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of ?18.3 dBm for a bit error rate = 10^?9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photo-current range from 12 to 500 μA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBΩ and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm² whereas the complete optical receiver occupies a chip area of 0.46 mm². The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.     

A 10 Gb/s 0.25 μm SiGe modulator driver for photonic-integration

A 10 Gb/s modulator driver in SiGe 0.25 μm BiCMOS technology with a chip area of only 0.54 mm² is presented. The intentions of designing this modulator driver are to amplify small incoming data signals at 10 Gb/s and to integrate the driver together with a silicon optical phase modulator (Mach–Zehnder modulator in push–pull configuration) on the same chip. The driver is designed to have a low power-consumption of 0.68 W but a high gain (S₂₁ = 37 dB). It consists of a differential pre-amplifier with common-mode feedback and automatic gain control, which is supplied by 2.5 V. The differential output stage is supplied with 3.5 V. The driver is designed to drive a Mach–Zehnder modulator, which uses in his arms carrier depletion in a reverse biased pn junction to adjust the refractive index. The differential output (5V_pp) delivers two times a voltage between 0 and 2.5 V. Therefore no bias-T is needed at the output to assure that the diodes of the interferometer arms are in the reverse biased mode. In addition to the low-power design, a passive network instead of an additional amplifier circuit for driving the cascode transistors, which reduce the collector–emitter voltage of each transistor in the output stage below breakdown, is presented. According to bit-error-ratio (BER) measurements with a pseudo-random-bit-sequence with the length of 2³¹ ? 1 the BER is better than 10^?12 for input voltage differences down to 50 mV_pp. The rise/fall time (20–80 %) is 45/30 ps respectively.     

An 8-bit 208 MS/s SAR ADC in 65 nm CMOS

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.     

An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors

This work proposes a 12 b 10 MS/s 0.11 μm CMOS successive-approximation register ADC based on a C-R hybrid DAC for low-power sensor applications. The proposed C-R DAC employs a 2-step split-capacitor array of upper seven bits and lower five bits to optimize power consumption and chip area at the target speed and resolution. A V_CM-based switching method for the most significant bit and reference voltage segments from an insensitive R-string for the last two least significant bits minimize the number of unit capacitors required in the C-R hybrid DAC. The comparator accuracy is improved by an open-loop offset cancellation technique in the first-stage pre-amp. The prototype ADC in a 0.11 μm CMOS process demonstrates the measured differential nonlinearity and integral nonlinearity within 1.18 LSB and 1.42 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 63.9 dB and a maximum spurious-free dynamic range of 77.6 dB at 10 MS/s. The ADC with an active die area of 0.34 mm² consumes 1.1 mW at 1.0 V and 10 MS/s, corresponding to a figure-of-merit of 87 fJ/conversion-step.     

A 360 fJ/conversion-step, 14-bit, 100 MS/s,digitally background calibrated pipelined ADC in 130-nm CMOS

This paper describes a 14-bit digitally background calibrated pipeline analog-to-digital converter (ADC) implemented in a mainstream 130-nm CMOS technology. The proposed calibration technique linearizes the digital output to correct for errors resulting from capacitor mismatch, finite amplifier gain, voltage reference errors and differential offsets. The software-based calibration technique requires quite modest digital resources and its estimated dynamic power is under 1 % of the ADC power consumption. After calibration, the 14-bit ADC achieves a measured peak Signal-to-Noise-plus-Distortion-Ratio of 71.1 dB at 100 MS/s sampling rate. The worst-case integral nonlinearity is improved from 32.9 down to 4 Least-Significant-Bits after calibration. The chip occupies an active area of 1.25 mm² and the core ADC (S/H+analog+digital power) consumes 105 mW. The Figure-of-Merit is 360 fJ per conversion-step.     

A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC

This work proposes a four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC based on various analog techniques to minimize mismatches between channels without any calibration scheme. The proposed ADC eliminates an input SHA to reduce offset mismatches, while the pipelined SAR architecture solves the problem of limited input bandwidth as observed in conventional SHA-free ADCs. In addition, a shared residue amplifier between four channels minimizes various mismatches caused by amplifiers in the first-stage MDACs. Two types of references for the residue amplifier and the SAR ADCs isolate the reference instability problem due to different functional requirements, while the shared residue amplifier uses only a single reference during the amplifying mode of each channel to reduce a gain mismatch. For high performance of the SAR ADC, high-frequency clocks with a controllable duty cycle are generated on chip without external, complicated, high-speed multi-phase clocks. The prototype 11 b ADC in a 0.13 μm CMOS shows a measured DNL and INL of 0.31 LSB and 1.18 LSB, respectively, with an SNDR of 59.3 dB and an SFDR of 67.7 dB at 100 MS/s, and an SNDR of 54.5 dB and an SFDR of 65.5 dB at 150 MS/s. The ADC with an active die area of 2.42 mm² consumes 46.8 mW at 1.2 V and 150 MS/s.     

A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference

This paper proposes a 10 b 120 MS/s CMOS ADC with a PVT-insensitive current reference. The designed current reference shows a mean temperature drift of 35.2 ppm/°C in the temperature range from −25 to 100°C and a supply rejection of 1.1%/V between 1.6 and 2.0 V. The prototype ADC fabricated in a 0.18 μm 1P6M CMOS technology demonstrates a measured DNL and INL of 0.18LSB and 0.53LSB with a maximum SNDR and SFDR of 53 and 68 dB at 120 MS/s. The ADC with an active chip area of 1.8 mm² consumes 108 mW at 120 MS/s and 1.8 V while the proposed on-chip current reference consumes 0.35 mW with a die area of 0.02 mm².     

A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 μm CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 × 280 μm².     

A broadband, differential transimpedance amplifier in 0.35 μm SiGe BICMOS technology for 10 Gbit/s fiber optical front-ends

This study focuses on 10 Gbit/s differential transimpedance amplifier. At the beginning of the work, the amplifier circuit is deeply analyzed and is optimized for the best phase linearity over the bandwidth resulted in a group delay variation less than 1 ps. The amplifier circuit is designed with 0.35 μm SiGe heterojunction bipolar transistor BICMOS process. 9 GHz bandwidth, almost 58 dBΩ transimpedance gain with less than 11.18 pA/ $ \sqrt {\text{Hz}} $ averaged input-referred noise current are achieved. Electrical sensitivity is 15 μA_pp. Power consumption is 71 mW at 3.3 V single power supply.     

A 7-bit 40 MS/s single-ended asynchronous SAR ADC in 65 nm CMOS

This paper presents a 7-bit 40 MS/s single-ended asynchronous SAR ADC intended for in-probe use in medical applications, which requires small area and good power efficiency. A single-ended architecture is proposed for a moderate resolution for its simplicity. Together with a double reference technique, the architecture reduces the area of the technology-limited large capacitors. The speed is optimized by an asymmetric delay line embedded in the asynchronous digital logic, enabling a sampling frequency of 40 MS/s. The prototype is fabricated in a 65 nm CMOS technology. Measurement shows that at 1 V supply and 40 MS/s, the ADC achieves an SNDR of 39.73 dB and an ENOB of 6.3 bit, while consuming 298.6 µW, resulting in an energy efficiency of 94.74 fJ/conversion-step. The core circuit layout only occupies 0.017 mm².     

An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm². The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm² fJ/conversion-step.     

A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system

In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding–interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.     

Low-power 10 Gb/s inductorless inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS

This study presents an inductorless 10 Gb/s transimpedance amplifier (TIA) implemented in a 40 nm CMOS technology. The TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows measured optical sensitivities of ?17.7 and ?16.2 dBm at BER = 10^?12 for data rates of 8 and 10 Gb/s, respectively. The TIA has a simulated transimpedance gain of 47 dBΩ, 8 GHz bandwidth with 0.45 pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002 mm² whereas the complete optical receiver occupies a chip area of 0.16 mm². The power consumption of the TIA is only 2.03 mW and the complete chip dissipates 17 mW for a 1.1 V single supply voltage. The complete optical receiver has a measured transimpedance gain of 57.5 dBΩ.     

10 Gb/s adaptive receive-side merged near-end and far-end crosstalk cancellation circuitry in 65 nm CMOS

Crosstalk between neighboring channels can have significant impact on system bit-error rate (BER) as serial I/O data rates scale above 10 Gb/s. This paper presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an on-die sign–sign least-mean-square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. A prototype fabricated in a general purpose 65-nm CMOS process includes the adaptive NEXT and FEXT circuitry, along with a continuous-time linear equalizer (CTLE) to compensate for frequency-dependent channel loss. Enabling the crosstalk cancellation circuitry while operating at 10 Gb/s over coupled 4-in FR4 transmission line channels with NEXT and FEXT aggressors opens a previously closed eye and allows for a 0.2 UI timing margin at a BER = 10^?9. Total power including the NEXT/FEXT crosstalk cancellation circuitry, CTLE, and high-speed output buffer is 34.6 mW, and the core circuit area occupies 0.3 mm².     

A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

This paper presents a 6-bit low power low supply voltage time-domain comparator. The conventional voltage comparison is moved to time-domain so as to remove pre-amplifier and latch, which enables its feasibility to low supply voltage. The voltage-to-time converter is realized by the proposed linear pulse-width-modulation. The set-up time of the D flip-flop determines the sampling rate of the converter. The resistive averaging relaxes the matching requirement of the parallel comparison cells. The total input capacitance is decreased to less than 40fF in this architecture. The above digital-intensive setting makes the analog-to-digital converter (ADC) benefit from technology scaling in both power consumption and sampling rate. The prototype ADC is fabricated in SMIC 0.18 μm CMOS process. At 40 MS/s and 1.0-V supply, it consumes 540 μW and achieves an effective-number-of-bit of 5.43, resulting in a figure-of-merit of 0.31 pJ/conversion-step and active area of 0.1 mm².     

A 1.5 V 10-b 30-MS/s CMOS pipelined analog-to-digital converter

A 1.5 V 10-b 30MS/s CMOS pipelined analog-to-digital converter (ADC) is described. Low-voltage techniques are proposed for pipelined analog-to-digital converter that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough and enhance the dynamic performance of the pipelined ADC. Multiplying digital-to-analog converter (MDAC) with cross-coupled configuration also provides an effective common-mode feedback to overcome the problem of common-mode accumulation. The prototype chips have been fabricated and experimental results confirm the feasibility of this new technique.     

40Gb/s,100Gb/s以太网IEEE P802.3ba标准研究

介绍了下一代以太网标准IEEE P802.3ba的研究进展、IEEE P802.3ba任务组关于速率的选择与应用目标的确定、协议结构和物理媒质相关特性.重点阐述其物理层的分层模型和工作原理,详细分析了协议的弹性和扩展性设计,并对标准的规模商用前景作了介绍.     

A 5 Gb/s multi-mode transmitter with de-emphasis for PCI Express 2.0/USB 3.0

A versatile transmitter compatible SERDES system was fabricated in 55 nm CMOS technology. The proposed transmitter comprises a low-power and low-area driver with de-emphasis and a 10:1 serializer, meanwhile it supports power management to reduce the unnecessary dissipation and to complete the mode transition among four power modes. Furthermore, the transmitter is compatible with PCI Express 2.0/1.0 and also meets the USB 3.0 standard. The experimental results show this test chip passes PCI Express 2.0/1.0 TX compliance test and USB 3.0 TX compliance test. The chip occupies 0.033 mm² and consumes 33 mA at 5 Gb/s.