基于形状工程的可靠磁性逻辑器件和触发器实现

纳米级磁性逻辑器件是一种新兴的场耦合计算范例,可用于实现非易失性和极低功耗的磁性逻辑电路.然而,杂散磁场和温度波动热效应阻碍了器件和电路的可靠转换.该文研究了对称缺失等腰三角形特殊形状纳磁体的转换特性,提出了利用这种特殊形状纳磁体实现磁性逻辑器件可靠转换的方法.基于特殊形状纳磁体器件设计了流水线RS触发器时序电路,并采用OOMMF软件进行了性能模拟.结果表明,特殊形状纳磁体实现的基本触发器电路不但能够进行可靠的流水线计算,同时还具有较高的工作温度和良好的按比例缩小特征.     

可配置的先进超低功耗逻辑解决方案

该系列器件由可配置逻辑门组成,这些逻辑门能够让单一双输入器件实现多项逻辑功能。74AUP系列能够实现多达9种不同的逻辑功能：与、与非、或、或非、异或、异或非、多路复用、反相器和缓冲器。     

Lattice pLSI器件与Altera EPM7000系列器件之比较

本文扼要地阐述Ｌａｔｔｉｃｅ的ｐＬＳＩ／ｉｓｐＬＳＩ１０００系列高密度可编程逻辑器件与Ａｌｔｅｒａ ＥＰＭ７０００系列多阵列矩阵（ＭＡＸ）器件在结构方面的差异，并指出使用ｐＬＳＩ／ｉｓｐＬＳＩ器件在下列关键结构方面要优直于ＥＰＭ７０００系列器件：－逻辑块尺寸－乘积项配置－输入数目与逻辑利用率－时钟－输出使能－Ｉ／Ｏ寄存器－布线与端口锁定的灵活性－制作工艺     

FPGA逻辑资源重配置测试技术研究

针对FPGA的逻辑资源测试,提出了一种内建自测试方法.测试中逻辑资源划分为不同功能器件,对应各个功能器件设计了相应的BIST测试模板.在此基础上进一步利用FPGA的部分重配置性能优化BIST测试过程,最终在统一的BIST测试框架下,采用相对较少的配置次数完成了逻辑资源固定故障的全覆盖测试.     

可编程逻辑器件在数字系统中的应用

介绍了可编程逻辑器件在数字信号处理系统中的应用。并运用VHDL语言对采用Lattice公司的ispLS11032E可编辑逻辑器件所构成的乘法器的结构、原理及各位加法器的VHDL作了详细的描述。该乘法器的最大特点是节省芯片资源,而且其运算速度取决于输入的时钟频率。     

量子元胞自动机共面五输入择多门结构的分析与设计

量子元胞自动机（Quantum-dot Cellular Automata,QCA）是一种具有新型计算范式的纳米器件,它是未来有望替代传统CMOS器件的有力竞争者之一.本文首先从QCA器件的功耗角度出发,对影响半径为41nm的QCA共面系统中元胞的耦合度进行建模,根据元胞之间的位置关系构造QCA门结构模型,据此对现有的共面五输入择多门进行分类,通过性能分析总结其结构特点,以此设计出一个新的低功耗五输入择多门,测试结果表明该结构功耗最低且其他性能也相对较优.另外,为验证所提出五输入择多门在电路中的性能,本文选择MR Azghadi全加器设计了一款共面QCA全加器,与同类加法器相比性能也最优.     

一种宽输入范围高精度频率计的设计

数字频率计设计一般都是采用分立数字器件和集成模拟芯片来实现,其精度不太高,而且输入信号范围常常受到限制.一种采用可编程数字逻辑器件CPLD,将数字器件进行集成化,并配备高稳定度时钟,对输入模拟信号采用多路程控精密放大整形的技术,利用等精度测频法,实现了对频率的高精度测量.使得频率测量范围达到数十兆,精度超过10-7,输入信号最小到10 mV.     

可编程模糊逻辑控制器芯片的设技

本文提出了一种由模拟电路实现的通用可编程模糊逻辑控制器（ＰＦＬＣ）,针对两输入变量、一输出变量的控制对象,允许有８１条控制规则,该控制器是由电流型ＣＭＯＳ多值器件构成,采用２μｍ标准ＣＭＯＳ工艺制造ＰＦＬＣ有方便的输入／输出接口和修改规则,其模糊推进过程是并行的,每时钟周期完成一次,最高时钟频率可达１ＭＨｚ。     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

在系统集成中的可编程器件（二）

带宏单元的复杂PLD—EPLD 简单PLD器件除了编程逻辑单元的门数比较少(在500个等效门以内)之外,通常它所实现的输入和输出的逻辑映射也比较简单,一般是组合逻辑形式的逻辑函数,此外多数早期PLD产品的编程元件也多为一次性的。为了克服上述问题,复杂PLD元件着重在两方面有改进:一是引进宏单元扩展逻辑功能单元的功能,例如对I/O端编程控制可扩大输入端数量;对输出形式编程控制可输出同步寄存方式和非同步组合方式的逻辑函数以及对输出反馈控制可实现较为复杂的逻辑函数。另一个改进是引入可重复编程的配置储存元件和开关元件,如EPROM和E~2PROM及其传输门互连开关。这种可重编辑元件占     

Clocking misalignment tolerance of pipelined magnetic QCA architectures

In this paper, we present a simulation study on clocking misalignment tolerance of pipelined magnetic quantum-dot cellular automata (MQCA) architectures. By the three-phase pipelined clocking and deduced clocking misalignment model, a systematic evaluation of impacts of clocking misalignment on four fundamental MQCA architectures is performed at non-zero temperatures. It is found that for the fixed nanomagnet size, majority logic gate is the most reliable structure, while the corner is most susceptible to clocking misalignment. High temperature gives rise to a negative effect on allowable misalignment angles. The results also show that as the aspect ratio of nanomagnet increases, the ability that all the MQCA architectures tolerate clocking misalignment decreases. Moreover, we analyze potential reason of pipelined MQCA architecture failures by examining the energy profile of neighboring zone nanomagnets and conclude that various energy barrier difference accounts for failure of MQCA architectures under clocking misalignment defect.     

Reliability analysis of magnetic logic interconnect wire subjected to magnet edge imperfections

Nanomagnet logic (NML) devices have been proposed as one of the best candidates for the next generation of integrated circuits thanks to its substantial advantages of nonvolatility,radiation hardening and potentially low power.In this article,errors of nanomagnetic interconnect wire subjected to magnet edge imperfections have been evaluated for the purpose of reliable logic propagation.The missing comer defects of nanomagnet in the wire are modeled with a triangle,and the interconnect fabricated with various magnetic materials is thoroughly investigated by micromagnetic simulations under different comer defect amplitudes and device spacings.The results show that as the defect amplitude increases,the success rate of logic propagation in the interconnect decreases.More results show that from the interconnect wire fabricated with materials,iron demonstrates the best defect tolerance ability among three representative and frequently used NML materials,also logic transmission errors can be mitigated by adjusting spacing between nanomagnets.These findings can provide key technical guides for designing reliable interconnects.     

Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)

Am-IDGFET is a new family of particular devices in view of the fact that it associates three benefits: (i) it is usually a 1-D electronic device (CNT or SiNW), meaning high mobility, achievable current density and high I_ON/I_OFF ratio; (ii) Independently controlled gates which offers the device extra logic options; (iii) ambipolar behaviour opens the way for N- and P-type polarities in the same device via its back gate. The creativity of this work consists of looking at this new class of emerging technology as an opportunity for new design paradigms with no equivalent counterparts in CMOS technology. Nevertheless, to build a feasible and complete picture of ambipolar logic, innovative design approaches and tools are required. In this paper, we exploit functional classification, a powerful tool for the construction and analysis of Boolean functions, to build reconfigurable logic blocks by defining a hierarchical correlation between structures of functions classes with ambipolar devices. We demonstrate how this approach enables us to build Am-I DGFET-based n-input reconfigurable cells. Several dynamically reconfigurable 2-inputs logic cells with partial and full functionality are designed in this paper. We evaluate the performances of circuits designed from this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Simulations results show efficiency to build fine grain reconfigurable cells with partial functionality. In the case of 9-functions reconfigurable cell, an improvement of 1.8X in terms of power delay product (PDP) is proved when compared to a CMOS-16 nm technology. Fewer control signals are required and the area is reduced by 35% over CMOS technology.     

倾斜边缘纳磁体对磁性量子元胞自动机互连线信号传递的影响

纳磁体倾斜边缘是磁性量子元胞自动机(Magnetic quantum cellular automata,MQCA)制备过程中常见的缺陷。研究倾斜边缘纳磁体的位置、缺失程度、形状等对互连线的影响,并分析了纳磁体间距和厚度对倾斜边缘MQCA互连线信号传递的影响。仿真结果得出,倾斜边缘对互连线的信号传递产生三种影响:正常、反向和中断。倾斜边缘的缺失尺寸越大,互连线的信号传递受到的影响越大;难磁化轴方向边缘完全缺失的情况下,较小的垂直缺失尺寸即可对互连线信号传递造成较大影响;较薄的厚度和较小的间距更有利于包含倾斜边缘纳磁纳磁体的互连线信号的正常传递。这些结论对于MQCA电路的制备、缺陷分析以及倾斜边缘纳磁体的特殊应用具有重要意义。     

并行可重构模糊控制器的在系统设计

为使模糊控制器具有计算并行性及在系统可重构性,通过系统可编程逻辑器件,采用自顶向下模块化方法,设计一种通用型模块化模糊控制器.按照功能要求对模糊控制器功能模块进行划分,并设计了各模块相应的逻辑结构,以及带有复位功能的模糊控制器的数字逻辑实现方案,然后设计了模糊控制器的VHDL程序.最后通过实验测试分析,验证了系统的可行性.     

Numerical Investigation of a 160-Gb/s Reconfigurable Photonic Logic Gate Based on Cross-Phase Modulation in Fibers

A simple reconfigurable all-optical logic gate based on cross-phase modulation in highly nonlinear fibers is numerically demonstrated. Fine performance at 160 Gb/s is obtained for five logic functions (xor, or, nand, nor and not). The implementation simplicity and the high-bit-rate operation make the proposed device suitable for ultrafast applications in the emerging all-optical networks     

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.     

Threshold logic circuit design of parallel adders using resonanttunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed     

一种基于多个级联微环的高速多功能电光逻辑门

设计了一种基于多个级联微环谐振器的多功能逻 辑门。通过选择不同的输入口和输出 口,可实现与门/非与门(AND/NOT)、或门/或非门(OR/NOR)和异或门/同或门(XOR/XNO R)6种不同的逻辑运算。每次改变输 入口,可同时在两个输出口得到两种不同的逻辑运算。利用电光效应良好的聚合物作为 微环材料,输入两组不同的电压信号,通过Simulink仿真得出不同输出口的输出光场,证 明了6种逻辑运算的可行性。与之前报道的微环逻辑门相比,本文设计的逻辑门可实现的 逻辑功能更多,响应时间更短,损耗更小,尺寸也更小。