基于混合遗传算法的模拟电路自动设计研究

模拟电路在电子系统设计中具有重要意义.模拟电路设计包括电路拓扑结构设计和元件值设计,这两个方面对计算机辅助模拟电路设计都很重要.但是,传统的遗传算法在不断进化电路元件值时效率低.因此,本文提出一种具有超突变和精英策略的混合遗传算法HME-GA.该方法不仅可以用来设计电路的拓扑结构,而且可用于设计电路的元件值.实验结果表明,HEM-GA算法优于简单遗传算法GA,可作为计算机辅助模拟电路设计的有效方法,在模拟电路自动化设计中具有非常重要的意义和巨大的应用潜力.     

基于矩阵编码的量子可逆逻辑电路进化设计方法

 本文研究基于遗传算法的量子可逆逻辑电路综合技术,能实现可逆逻辑电路功能、量子门数、垃圾位数和量子代价的多目标优化设计.建立了量子可逆逻辑电路综合数学模型,采用了量子可逆逻辑电路矩阵编码方案,设计了量子可逆逻辑电路进化操作算子,给出了量子可逆逻辑电路多目标进化设计算法.以8位量子可逆乘法器为设计实例,实验结果证明了所提出的量子可逆逻辑电路多目标进化设计方法是正确有效的.     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

Analog circuit optimization system based on hybrid evolutionary algorithms

This paper investigates a hybrid evolutionary-based design system for automated sizing of analog integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through electrical simulation, to the optimization system in the MATLAB environment, once a circuit topology is selected. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met, even in highly-constrained situations. Comparisons with available methods like genetic algorithms and differential evolution, which use static penalty functions to handle design constraints, have also been carried out, showing that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.     

基于自适应遗传算法的模拟电路自动设计方法

针对电路进化设计的速度和规模瓶颈,提出并讨论一种新的自适应遗传算法,其特点包括:支持结构自动生成和元件参数标准化的编解码方案,兼顾功能设计和结构化简要求的多目标适应度评估,考虑基因位影响力并跟踪进化进程的遗传参数调整策略等.实验证明,该方法可自动生成电路结构、优化元件参数和化简电路,并显著地减小运算量和提高优化程度.     

MOS current mode circuits: analysis, design, and variability

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.     

SOI在射频电路中的应用

随着射频电路(RF)工作频率和集成度的提高,衬底材料对电路性能的影响越来越大.SOI(Silicon-on-Insulator)结构以其良好的电学性能,为系统设计提供了灵活性.与CMOS工艺的兼容使它能将数字电路与模拟电路混合,在射频电路应用方面显示巨大优势.文章分析了RF电路发展中遇到的挑战和SOI在RF电路中的应用优势,综述了SOI RF电路的最新进展.     

SPICE modeling of process variation using location depth corner models

For robust designs, the influence of process variations has to be considered during circuit simulation. We propose a nonparametric statistical method to find sets of simulation parameters that cover the process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors using a location depth algorithm. The e-test corner vectors are then transformed to SPICE parameter vectors by a linear mapping. A special corner extension algorithm makes the resulting simulation setup robust against moderate process shifts while preserving the underlying correlation structure. To be applicable in a production and circuit design environment, the models are integrated into an automated model generation flow for usage within a design-framework. The statistical methods are validated for analog/mixed-signal benchmark circuits.     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

基于均匀设计的多目标自适应遗传算法及应用

提出一种多目标遗传算法,将均匀设计技术应用于适应度函数合成和交叉算子构造,以提高遗传算法的空间搜索均匀性、子代质量和运算效率.分析和实验结果表明,该方法可缩短算法运行时间和得到分布较均匀的Pareto有效解集;配合基于元件标称值的网表级高效编码方案和考虑基因位差异的遗传概率调整策略,可实现模拟电路自动设计,通过单次运行即获得对应不同偏好的多种实用化设计结果.     

CMOS analog/digital circuit of the hysteresis McCulloch-Pitts neuron for Ramsey numbers

A parallel algorithm for finding Ramsey numbers is presented where analog/digital CMOS circuits for the hysteresis McCulloch-Pitts binary neuron are described. The hysteresis McCulloch-Pitts binary neuron model is used in order to suppress the oscillatory behaviors of neural dynamics so that the convergence time is shortened. The proposed algorithm using the hysteresis McCulloch-Pitts binary neuron found five Ramsey numbers. The analog CMOS sigmoid circuit with variable gain controls has been fabricated and tested using the SAC data acquisition board interfaced with a TMS 32010 processor. Hysteresis can be implemented by the positive feedback in the fabricated CMOS analog circuit.     

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.     

Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits

This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters' variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation CMOS current conveyor and a CMOS voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.     

State of the art in the analog CMOS circuit design

This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.     

基于CMOS模拟电路的高速模糊神经网络设计

本文提出了可构成多规则模糊神经网络的CMOS模拟单元电路,包括:类Gauss型隶属度函数电路,电压求小电路和重心算法去模糊电路.基于这些电路设计了一个两输入/一输出、25条规则的控制系统,并通过非线性函数逼近进行了验证.所有单元均采用SMIC 0.18-μm CMOS数模混合工艺制造,芯片测试结果表明:提出的单元电路结构简单,输出电压偏差小,便于扩展和调节;因而适于实现多规则,自适应调节的高速高精度控制系统.     

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S²I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance     

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density